公开(公告)号：DE112013001941T5

公开(公告)日：2014-12-24

申请号：DE112013001941

申请日：2013-05-17

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

IPC: G06F9/38 ,  G06F9/52

Abstract: Eingeschränkten Anweisungen ist eine Ausführung in einer Transaktion untersagt. Es gibt Klassen von Anweisungen, die ohne Berücksichtigung des Transaktionstyps eingeschränkt sind: eingeschränkt oder nicht eingeschränkt. Es gibt Anweisungen, die nur in eingeschränkten Transaktionen eingeschränkt sind, und es gibt Anweisungen, die selektiv eingeschränkt sind für bestimmte Transaktionen auf der Grundlage von Steuerelementen, die in Anweisungen angegeben sind, die zum Einleiten der Transaktionen verwendet werden.

公开(公告)号：AU2012382779A1

公开(公告)日：2014-12-11

申请号：AU2012382779

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN

IPC: G06F12/00

Abstract: Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt.

公开(公告)号：AU2012382776A1

公开(公告)日：2014-12-11

申请号：AU2012382776

申请日：2012-11-22

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

IPC: G06F9/46

Abstract: A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include user-specified information that may facilitate debugging of an aborted transaction.

公开(公告)号：MX2014010946A

公开(公告)日：2014-11-13

申请号：MX2014010946

申请日：2012-11-15

Applicant: IBM

Inventor： SLEGEL TIMOTHY ,  SCHWARZ ERIC MARK ,  BRADBURY JONATHAN DAVID ,  GSCHWIND MICHAEL KARL ,  JACOBI CHRISTIAN

IPC: G06F12/10

Abstract: Se provee una instrucción de carga a frontera de bloque que carga un número variable de bytes de datos a un registro mientras que asegura que no se cruce una frontera de memoria especificada. La frontera puede ser especificada de una diversidad de maneras, incluyendo pero no limitado a un valor variable en el texto de instrucción, un valor de texto de instrucción fijo codificada en el código de operación o una frontera a base de registro.

公开(公告)号：SG11201404822XA

公开(公告)日：2014-09-26

申请号：SG11201404822X

申请日：2012-11-15

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID ,  GSCHWIND MICHAEL KARL ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN

IPC: G11C11/00

Abstract: A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.

公开(公告)号：CA2874236A1

公开(公告)日：2013-12-19

申请号：CA2874236

申请日：2013-06-12

Applicant: IBM

Inventor： GREINER DAN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY

IPC: G06F9/30 ,  G06F12/00

Abstract: A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block.

公开(公告)号：CA2874181A1

公开(公告)日：2013-12-19

申请号：CA2874181

申请日：2012-11-26

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN

IPC: G06F9/30 ,  G06F12/00

Abstract: Constrained transactional processing is provided. A constrained transaction is initiated by execution of a Transaction Begin constrained instruction. The constrained transaction has a number of restrictions associated therewith. Absent violation of a restriction, the constrained transaction is to complete. If an abort condition is encountered, the transaction is re-executed starting at the Transaction Begin instruction. Violation of a restriction may cause an interrupt.

公开(公告)号：CA2867088A1

公开(公告)日：2013-09-19

申请号：CA2867088

申请日：2012-11-15

Applicant: IBM

Inventor： BRADBURY JONATHAN DAVID ,  GSCHWIND MICHAEL KARL ,  SLEGEL TIMOTHY ,  SCHWARZ ERIC MARK ,  JACOBI CHRISTIAN

IPC: G06F9/34

Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.

公开(公告)号：GB2486155A

公开(公告)日：2012-06-06

申请号：GB201206367

申请日：2010-12-13

Applicant: IBM

Inventor： JACOBI CHRISTIAN ,  THOMPTO BRIAN WILLIAM ,  ALEXANDER GREGORY WILLIAM ,  ALEXANDER KHARY JASON ,  CURRAN BRIAN WILLIAM ,  MITCHELL JAMES RUSSELL ,  HSIEH JONATHAN TING ,  PRASKY BRIAN ROBERT

IPC: G06F9/38

Abstract: A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

公开(公告)号：GB2456405B

公开(公告)日：2012-05-02

申请号：GB0822457

申请日：2008-12-10

Applicant: IBM

Inventor： JACOBI CHRISTIAN ,  FABEL SIMON ,  PFLANZ MATTHIAS ,  TAST HANS-WERNER ,  ULRICH HANNO

IPC: G06F12/08 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0893