公开(公告)号：US08263875B2

公开(公告)日：2012-09-11

申请号：US11901078

申请日：2007-09-13

Applicant: Takamasa Nodo ,  Haruo Takagi

Inventor： Takamasa Nodo ,  Haruo Takagi

IPC: H05K1/16

CPC classification number: H05K1/111 ,  H05K3/3442 ,  H05K2201/09254 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/09727 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: A surface mounting structure for a surface mounting electronic component has an electronic component, a land, a wiring, and an electrical connection pattern. The electronic component has electrodes at opposite ends thereof. The land is connected to each electrode through a solder. The wiring is connected to the land and has a width which is smaller than a width of the electronic component in a width direction thereof. The wiring is connected to the electrical connection pattern. The electrical connection pattern has on a side on which the wiring is connected to the electrical connection pattern a width which is larger than the width of the electronic component in the width direction thereof.

Abstract translation: 用于表面安装电子部件的表面安装结构具有电子部件，焊盘，布线和电连接图案。 电子部件在其相对端具有电极。 焊盘通过焊料连接到每个电极。 布线连接到台面，其宽度小于电子部件的宽度方向的宽度。 接线连接到电气连接图案。 电连接图案具有在电连接图案的与电子部件的宽度方向的宽度大的宽度上连接的一侧。

公开(公告)号：US08013691B2

公开(公告)日：2011-09-06

申请号：US12224133

申请日：2007-02-28

Applicant: Takashi Okano

Inventor： Takashi Okano

IPC: H03H7/00

CPC classification number: H05K1/0231 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H05K1/0216 ,  H05K1/0233 ,  H05K1/181 ,  H05K2201/086 ,  H05K2201/09281 ,  H05K2201/10522 ,  H05K2201/10689 ,  H01L2924/00012

Abstract: One end of a power-supply bus is connected to a power supply through a ferrite bead. The power-supply bus is connected to power-supply terminals. The power-supply terminals are connected at positions in such a manner that a terminal with a higher intensity is connected closer to the other end of the power-supply bus. Ground terminals are connected to ground. Capacitors are bypass capacitors or decoupling capacitors, for example, and connected between respective power-supply terminals and ground.

Abstract translation: 电源总线的一端通过铁氧体磁珠连接到电源。 电源总线连接到电源端子。 电源端子以这样的方式连接，使得具有较高强度的端子更靠近电源总线的另一端连接。 接地端子接地。 例如，电容器是旁路电容器或去耦电容器，并且连接在相应的电源端子和地之间。

公开(公告)号：US20090166075A1

公开(公告)日：2009-07-02

申请号：US12344250

申请日：2008-12-25

Applicant: FA-PING FAN

Inventor： FA-PING FAN

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09281 ,  Y02P70/611

Abstract: An exemplary printed circuit board includes a substrate, a differential transmission line, and at least two weld pad pairs. The differential transmission line and the at least two weld pad pairs are disposed on the substrate. The differential transmission line includes two parallel signal conductors disposed on the substrate. Each of the two signal conductors is electrically connected to an edge of one of the weld pads of a respective pair of the at least two weld pad pairs. Thereby, the two signal conductors of the differential transmission line can extend in the same distance anywhere, particularly in the position where the two signal conductors pass the two weld pad pairs. As a result, the coupling performance and the capability of the differential transmission line to resist electromagnetic interference are both enhanced.

Abstract translation: 示例性印刷电路板包括基板，差分传输线和至少两个焊盘对。 差分传输线和至少两个焊盘对设置在基板上。 差分传输线包括设置在基板上的两个并行信号导体。 两个信号导体中的每一个电连接到相应的一对至少两个焊盘对的焊接焊盘之一的边缘。 因此，差分传输线的两个信号导体可以在任何地方延伸相同的距离，特别是在两个信号导体通过两个焊盘对的位置。 结果，提高了耦合性能和差动传输线抵抗电磁干扰的能力。

公开(公告)号：US07423221B2

公开(公告)日：2008-09-09

申请号：US11517786

申请日：2006-09-08

Applicant: Yoshinari Matsuda

Inventor： Yoshinari Matsuda

IPC: H05K1/16

CPC classification number: H05K3/3452 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: A printed wiring board on which a pattern can be formed favorably by printing and soldering even where a small part of the 1005 size or less is mounted. The printed wiring board includes a substrate; a pair of soldering lands on the substrate, the soldering lands being spaced from one another with a first side of one land opposing a first side of another land; and a mounted part having a pair of electrodes on opposite ends thereof soldered to the respective lands. A wiring line is connected to each soldering land, and an insulating element overlies the wiring lines. The insulating element has openings formed so as to expose the soldering lands therethrough. Wiring line connection elements are individually connected to only the first sides of the lands. Each insulating element opening has an edge positioned outside of the corresponding land and on the inner side of the corresponding wiring line connection element.

Abstract translation: 即使安装有小于1005的小部分，也可以通过印刷和焊接而形成图案的印刷电路板。 印刷线路板包括基板; 在基板上的一对焊接区域，所述焊接区域彼此间隔开，其中一个焊盘的第一面与另一焊盘的第一面相对; 以及其相对端上具有一对电极的安装部分焊接到相应的焊盘。 布线与每个焊接区连接，绝缘元件覆盖在布线上。 绝缘元件具有形成为暴露焊接区域的开口。 连接线连接元件仅分别连接到焊盘的第一侧。 每个绝缘元件开口具有位于对应的焊盘外侧和相应的布线连接元件的内侧的边缘。

公开(公告)号：US20070114057A1

公开(公告)日：2007-05-24

申请号：US11517786

申请日：2006-09-08

Applicant: Yoshinari Matsuda

Inventor： Yoshinari Matsuda

IPC: H05K1/16

CPC classification number: H05K3/3452 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: A printed wiring board on which a pattern can be formed favorably by printing and soldering even where a small part of the 1005 size or less is mounted. The printed wiring board includes a substrate; a pair of soldering lands on the substrate, the soldering lands being spaced from one another with a first side of one land opposing a first side of another land; and a mounted part having a pair of electrodes on opposite ends thereof soldered to the respective lands. A wiring line is connected to each soldering land, and an insulating element overlies the wiring lines. The insulating element has openings formed so as to expose the soldering lands therethrough. Wiring line connection elements are individually connected to only the first sides of the lands. Each insulating element opening has an edge positioned outside of the corresponding land and on the inner side of the corresponding wiring line connection element.

Abstract translation: 即使安装有小于1005的小部分，也可以通过印刷和焊接而形成图案的印刷电路板。 印刷线路板包括基板; 在基板上的一对焊接区域，所述焊接区域彼此间隔开，其中一个焊盘的第一面与另一焊盘的第一面相对; 以及其相对端上具有一对电极的安装部分焊接到相应的焊盘。 布线与每个焊接区连接，绝缘元件覆盖在布线上。 绝缘元件具有形成为暴露焊接区域的开口。 连接线连接元件仅分别连接到焊盘的第一侧。 每个绝缘元件开口具有位于对应的焊盘外侧和相应的布线连接元件的内侧的边缘。

公开(公告)号：US20070069834A1

公开(公告)日：2007-03-29

申请号：US11335195

申请日：2006-01-19

Applicant: Takanori Ikuta ,  Wataru Koga ,  Hiroki Kan ,  Yuuko Yokota

Inventor： Takanori Ikuta ,  Wataru Koga ,  Hiroki Kan ,  Yuuko Yokota

IPC: H03H9/70

CPC classification number: H05K1/0243 ,  H01L21/4853 ,  H01L2224/16225 ,  H05K1/0219 ,  H05K1/111 ,  H05K1/117 ,  H05K3/429 ,  H05K2201/09281 ,  H05K2201/09418 ,  H05K2201/09572 ,  H05K2201/09618 ,  H05K2201/0979 ,  H05K2201/09809 ,  H05K2201/10189 ,  Y02P70/611

Abstract: Terminal electrodes 9 for carrying a high frequency device 3 are formed on a surface of a circuit board having its reverse surface covered with a reverse surface conductor layer 6, and a plurality of signal lines 2 for exchanging a signal between the high frequency device 3 and an external circuit are formed thereon. The terminal electrode 9 is arranged at the center of the circuit board, and the signal lines 2 radially extends from the terminal electrode 9. Electromagnetic interference between the signal lines 2 can be reduced, so that out-of-band attenuation characteristics and isolation characteristics can be satisfactorily exhibited in a case where the high frequency device 3 is a duplexer.

Abstract translation: 用于承载高频器件3的端子电极9形成在电路板的表面，其表面覆盖有反面导体层6，并且多个信号线2用于在高频器件3和 在其上形成外部电路。 端子电极9布置在电路板的中心，信号线2从端子电极9径向延伸。 可以减小信号线2之间的电磁干扰，从而在高频装置3为双工器的情况下，可以令人满意地表现出带外衰减特性和隔离特性。

公开(公告)号：US20060261825A1

公开(公告)日：2006-11-23

申请号：US11217658

申请日：2005-08-31

Applicant: Shin-Shing Jiang ,  Sheng-Yuan Lee

Inventor： Shin-Shing Jiang ,  Sheng-Yuan Lee

IPC: G01R31/02

CPC classification number: H01R12/58 ,  H01R12/7064 ,  H01R24/50 ,  H01R2103/00 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0243 ,  H05K1/116 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/09281 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/09809 ,  H05K2201/10189

Abstract: A signal transmission structure for connecting a coaxial cable connector is provided. The coaxial cable connector has a signal pin. The signal transmission structure includes a reference plane and a conductive layer, and the conductive layer is located on one side of the reference plane. Moreover, the conductive layer includes a signal perforated pad, a first line segment, a second line segment, and a compensation pad. The signal pin is suitable for threading the signal perforated pad. The first line segment is connected to the signal perforated pad, and the compensation pad is connected between the first line segment and the second line segment.

Abstract translation: 提供了用于连接同轴电缆连接器的信号传输结构。 同轴电缆连接器有一个信号引脚。 信号传输结构包括参考平面和导电层，并且导电层位于参考平面的一侧。 此外，导电层包括信号穿孔垫，第一线段，第二线段和补偿垫。 信号针适用于信号穿孔垫的穿线。 第一线段连接到信号穿孔焊盘，补偿焊盘连接在第一线段和第二线段之间。

公开(公告)号：US20060054348A1

公开(公告)日：2006-03-16

申请号：US11162411

申请日：2005-09-09

Applicant: Jia-Cheng Chen ,  Yi-Chuan Ding

Inventor： Jia-Cheng Chen ,  Yi-Chuan Ding

IPC: H05K7/06

CPC classification number: H05K3/242 ,  H05K3/0044 ,  H05K3/28 ,  H05K2201/09281 ,  H05K2203/0228 ,  H05K2203/175

Abstract: A circuit substrate comprising a base and a plurality of conductive traces is provided. The conductive traces are disposed on the base and on the same layer. The conductive traces include at least one first conductive trace. Wherein, the base has a cut region. The end of the first conductive trace is connected to the end portion of the cut region. The included angle between the rim of the end portion of the cut region and the first conductive trace is 75° to 105°.

Abstract translation: 提供了包括基底和多个导电迹线的电路基板。 导电迹线设置在基底和同一层上。 导电迹线包括至少一个第一导电迹线。 其中，基地有一个切割区域。 第一导电迹线的端部连接到切割区域的端部。 切割区域的端部边缘与第一导电迹线之间的夹角为75°至105°。

公开(公告)号：US06686808B1

公开(公告)日：2004-02-03

申请号：US09329343

申请日：1999-06-10

Applicant: Satoru Sugawara ,  Koji Mizuno

Inventor： Satoru Sugawara ,  Koji Mizuno

IPC: H01P308

CPC classification number: H05K1/0242 ,  H01P1/211 ,  H01P3/026 ,  H05K1/0216 ,  H05K1/0219 ,  H05K2201/09236 ,  H05K2201/09281 ,  H05K2201/09727

Abstract: A coplanar stripline is provided, including a dielectric substrate, and first and second strip conductors, which are each formed on the dielectric substrate, parallel to each other and separated by a predetermined distance. The corrugated structure is formed at least on one side of the strip conductors, including a plurality of slits. The slits are formed periodically on the side of each of the strip conductors, which is located in the outside portion thereof and not facing the other confronting strip conductor, so that the length direction of the slit is substantially perpendicular to the direction of the electromagnetic wave transmitted through the coplanar stripline.

Abstract translation: 提供共面带状线，包括电介质基板和第一和第二条状导体，它们各自形成在电介质基板上，彼此平行并分开预定距离。 波纹结构形成在带状导体的至少一侧，包括多个狭缝。 这些狭缝在位于其外侧部分的每个条状导体的侧面周期性地形成，并且不面向另一个相对的带状导体，使得狭缝的长度方向基本上垂直于电磁波的方向 通过共面带状线传输。

公开(公告)号：US06538305B2

公开(公告)日：2003-03-25

申请号：US09912887

申请日：2001-07-25

Applicant: Michihiko Ichinose

Inventor： Michihiko Ichinose

IPC: H01L23495

CPC classification number: H05K3/3436 ,  H01L21/4853 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/28 ,  H05K2201/09263 ,  H05K2201/09281 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes an interposing substrate having a top surface mounting thereon a semiconductor chip and a bottom surface mounting thereon a solder ball islands. Chip electrodes of the semiconductor chip are connected to the solder ball islands through a top interconnect pattern, via holes and a bottom interconnect pattern. The second interconnect pattern has a solder-flow damping/stopping pattern in the vicinity of the solder ball islands for stopping the solder from flowing onto the bottom interconnect pattern upon melting.