公开(公告)号：WO2002095800A2

公开(公告)日：2002-11-28

申请号：PCT/US2002/016224

申请日：2002-05-22

Applicant: REFLECTIVITY, INC. ,  PATEL, Satyadev, R. ,  HUIBERS, Andrew, G. ,  SCHAADT, Gregory, P. ,  HEUREUX, Peter, J.

Inventor： PATEL, Satyadev, R. ,  HUIBERS, Andrew, G. ,  SCHAADT, Gregory, P. ,  HEUREUX, Peter, J.

IPC: H01L

CPC classification number: B81C1/00476 ,  B81C1/00547 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/112 ,  B82Y30/00

Abstract: An etching method, such as for forming a micromechanical device, is disclosed. One embodiment of the method is for releasing a micromechanical structure, comprising, providing a sacrificial layer directly or indirectly on the substrate; providing one or more micromechanical structural layers on the sacrificial layer; performing a first etch to remove a portion of the sacrificial layer, the first etch comprising providing an etchant gas and energizing the etchant gas so as to allow the etchant gas to physically, or chemically and physically, remove the portion of the sacrificial layer; performing a second etch to remove additional sacrificial material in the sacrificial layer, the second etch comprising providing a gas that chemically but not physically etches the additional sacrificial material. Another embodiment of the method is for etching a silicon material on or within a substrate, comprising: performing a first etch to remove a portion of the silicon, the first etch comprising providing an etchant gas and energizing the etchant gas so as to allow the etchant gas to physically, or chemically and physically, remove the portion of silicon; performing a second etch to remove additional silicon, the second etch comprising providing an etchant gas that chemically but not physically etches the additional silicon.

Abstract translation: 公开了一种诸如用于形成微机械装置的蚀刻方法。 该方法的一个实施例是用于释放微机械结构，其包括：在衬底上直接或间接提供牺牲层; 在所述牺牲层上提供一个或多个微机械结构层; 执行第一蚀刻以去除牺牲层的一部分，所述第一蚀刻包括提供蚀刻剂气体并激发蚀刻剂气体，以允许蚀刻剂气体在物理或化学和物理上去除牺牲层的该部分; 执行第二蚀刻以去除牺牲层中的附加牺牲材料，第二蚀刻包括提供化学上但不物理蚀刻附加牺牲材料的气体。 该方法的另一实施例是用于在衬底上或衬底内蚀刻硅材料，包括：执行第一蚀刻以去除硅的一部分，第一蚀刻包括提供蚀刻剂气体并激发蚀刻剂气体以允许蚀刻剂 物理或化学和物理的气体去除硅的部分; 执行第二蚀刻以去除附加的硅，第二蚀刻包括提供蚀刻剂气体，其化学地但不物理地蚀刻附加的硅。

公开(公告)号：WO2002073314A1

公开(公告)日：2002-09-19

申请号：PCT/US2002/007484

申请日：2002-03-12

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY ,  SCHERER, Axel

Inventor： SCHERER, Axel

IPC: G03F7/00

CPC classification number: B82Y10/00 ,  B81C1/00404 ,  B81C2201/0132 ,  G03F7/16 ,  Y10S977/72 ,  Y10S977/742 ,  Y10S977/887

Abstract: The invention is directed to a method of fabricating sub-wavelength features in semiconductors and insulators by starting with optical lithography patterns defined in a resist and then employing shadow-evaporation and directional etching to define nanoscale features. The directionality of this process is used together with a carefully defined photoresist mask to define an ion etching mask which allows the formation of very narrow trenches adjacent to the photoresist regions. Such narrow trenches can be used for electrical device isolation, for the definition of very small flow channels, and for the deposition of very narrow electrical contacts and wires.

Abstract translation: 本发明涉及一种在半导体和绝缘体中制造亚波长特征的方法，其方法是从抗蚀剂中定义的光刻图案开始，然后采用阴影蒸发和定向蚀刻来定义纳米尺度特征。 该方法的方向性与精心限定的光致抗蚀剂掩模一起使用以限定离子蚀刻掩模，其允许形成与光致抗蚀剂区域相邻的非常窄的沟槽。 这种窄沟槽可以用于电气设备隔离，用于定义非常小的流动通道，以及用于沉积非常窄的电触点和电线。

公开(公告)号：WO2002059939A2

公开(公告)日：2002-08-01

申请号：PCT/US2001/051193

申请日：2001-11-13

Applicant: THE JOHNS HOPKINS UNIVERSITY ,  MARTIN, Mark N,

Inventor： MARTIN, Mark N,

IPC: H01L

CPC classification number: B81C1/00476 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81C2201/0132 ,  B81C2203/0136 ,  H01L21/32135 ,  H01L29/84 ,  Y10T428/24996

Abstract: A process for fabricating a semiconductor device having, for example, a MISFET transistor, is provided which comprises the steps of (a) providing a partially fabricated semiconductor device comprising a substrate and a first and second polysilicon layer insulatively spaced from the substrate by an insulating layer, the insulating layer having an opening therein which exposes the surface of the first polysilicon layer positioned below the second polysilicon layer and (b) exposing the partially fabricated semiconductor device to a noble gas halide to substantially remove the first polysilicon layer.

Abstract translation: 提供一种用于制造具有例如MISFET晶体管的半导体器件的工艺，其包括以下步骤：（a）提供部分制造的半导体器件，其包括衬底和通过绝缘体与衬底绝缘间隔开的第一和第二多晶硅层 层，其中具有开口的绝缘层暴露位于第二多晶硅层下方的第一多晶硅层的表面，和（b）将部分制造的半导体器件暴露于惰性气体卤化物以基本上去除第一多晶硅层。

公开(公告)号：WO02054475A1

公开(公告)日：2002-07-11

申请号：PCT/US2002000015

申请日：2002-07-11

IPC: B81C1/00 ,  H01L21/46 ,  C23F1/00

CPC classification number: B81C1/00119 ,  B81B2201/0235 ,  B81C1/00357 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/019 ,  B81C2201/0191

Abstract: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI). One first obtains an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer. A mesa etch has been made on the device layer of the SOI wafer and a structural etch has been made on the dielectric layer of the SOI wafer. One then obtains a substrate (such as glass or silicon), where a pattern has been etched onto the substrate. The SOI wafer and the substrate are bonded together. Then the handle layer of the SOI wafer is removed, followed by the dielectric layer of the SOI wafer.

Abstract translation: 本发明提供了使用绝缘体上硅（SOI）制造微电子机械系统（MEMS）和相关器件的一般制造方法。 首先获得具有（i）手柄层，（ii）介电层和（iii）器件层）的SOI晶片。 已经在SOI晶片的器件层上进行了台面蚀刻，并且在SOI晶片的电介质层上进行了结构蚀刻。 然后，获得衬底（例如玻璃或硅），其中已将图案蚀刻到衬底上。 SOI晶片和衬底结合在一起。 然后去除SOI晶片的手柄层，随后是SOI晶片的电介质层。

公开(公告)号：WO01063657A1

公开(公告)日：2001-08-30

申请号：PCT/US2001/005949

申请日：2001-02-22

IPC: B81C1/00 ,  H01L21/3065 ,  H01L21/3213

CPC classification number: H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89 DEG +/-1 DEG sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

Abstract translation: 描述了用于蚀刻作为掩模结构的一部分的层的两种蚀刻剂蚀刻方法。 该方法例如在微电机械系统（MEMS）应用中以及集成电路和其它电子设备的制造中是有用的。 该方法可以有利地用于优化等离子体蚀刻工艺，该等离子体蚀刻工艺能够在形成为掩模结构的掩模结构的一部分的硅层中蚀刻严格的具有89°+/- 1°侧壁的轮廓控制沟槽，其中掩模结构引起蚀刻速率的变化。 本发明的两种蚀刻剂蚀刻方法蚀刻具有第一蚀刻剂蚀刻的结构中的层，直到蚀刻最快蚀刻区域中的层。 然后用第二蚀刻剂蚀刻该层，直到蚀刻具有最慢蚀刻速率的区域中的层。 还可以选择第二蚀刻剂以向结构的下层提供侧壁钝化和选择性。

公开(公告)号：WO99062684A1

公开(公告)日：1999-12-09

申请号：PCT/US1999/012324

申请日：1999-06-03

IPC: B29C33/42 ,  B81C1/00 ,  B81C99/00 ,  B29C39/02 ,  B29C41/08 ,  B44C1/22 ,  C23F1/02 ,  C23F1/04

CPC classification number: B81C99/009 ,  B81C99/0085 ,  B81C2201/0132 ,  B81C2201/034

Abstract: A method for molding high precision components (112) is provided that allows fabrication of components (112) using a process involving a silicon substrate (100), in which the mold pattern (104 and 108) is created using multiple mask layers (102 and 106), a deep reactive ion etch process and photolithographic patterning techniques.

Abstract translation: 提供了一种用于模制高精度部件（112）的方法，其允许使用涉及硅衬底（100）的工艺来制造部件（112），其中使用多个掩模层（102和102）形成模具图案（104和108） 106），深反应离子蚀刻工艺和光刻图案化技术。

公开(公告)号：EP3210937A1

公开(公告)日：2017-08-30

申请号：EP17158214.1

申请日：2017-02-27

Applicant: SmartTip B.V.

Inventor： SARAJLIC, Edin

IPC: B81C1/00 ,  A61B5/15

CPC classification number: B81C1/0015 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150396 ,  A61B5/150511 ,  A61B5/150519 ,  A61B5/150984 ,  A61B5/15142 ,  A61M37/0015 ,  B81B2201/057 ,  B81B2201/12 ,  B81B2203/0118 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00111 ,  B81C1/00119 ,  B81C2201/0132 ,  B81C2201/0143 ,  B81C2201/0159 ,  B81C2201/0198 ,  C01B21/0687

Abstract: A method of manufacturing a plurality of through-holes (132) in a layer of first material, for example for the manufacturing of a probe (100) comprising a tip containing a channel. To manufacture the through-holes (132) in a batch process,
- a layer of first material is deposited on a wafer (200) comprising a plurality of pits (210)
- a second layer is provided on the layer of first material, and the second layer is provided with a plurality of holes at central locations of the pits (210);
- using the second layer as a shadow mask when depositing a third layer (240) at an angle, covering a part of the first material with said third material (240) at the central locations, and
- etching the exposed parts of the first layer using the third layer (240) as a protective layer.

Abstract translation: 一种在第一材料层中制造多个通孔（132）的方法，例如用于制造包括包含通道的尖端的探针（100）。 为了以间歇工艺制造通孔（132）， - 在包括多个凹坑（210）的晶片（200）上沉积第一材料层 - 在第一材料层上提供第二层，以及 第二层在凹坑（210）的中心位置设置有多个孔; - 当以一定角度沉积第三层（240）时，使用第二层作为阴影掩模，在中心位置处用所述第三材料（240）覆盖第一材料的一部分，以及 - 蚀刻第一层 使用第三层（240）作为保护层。

公开(公告)号：EP3196617A1

公开(公告)日：2017-07-26

申请号：EP17150950.8

申请日：2017-01-11

Applicant: Rosemount Aerospace Inc.

Inventor： ZHANG, Weibin ,  POTASEK, David P.

IPC: G01L9/00 ,  G01L19/06

CPC classification number: B81B3/0021 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C2201/0132 ,  B81C2201/0133 ,  G01L9/0048 ,  G01L19/0618

Abstract: A method for producing a silicon based MEMS pressure sensor includes forming a cavity in a first (100) surface of a silicon wafer with first and second parallel (100) surfaces wherein the angle between the walls of the first cavity and the first (100) surface where they intersect the first (100) surface are greater than 90 degrees and the remaining material between the bottom of the cavity and the second parallel (100) surface comprises a flexible diaphragm. The method also includes forming a backing wafer, having a through hole, and bonding the silicon wafer to the backing wafer such that the hole in the backing wafer matches up with the cavity in the second side of the (100) silicon wafer. A dielectric layer is formed on the second side of the (100) silicon wafer and a sensing element is formed on the dielectric layer to detect pressure induced deflection of the silicon diaphragm.

Abstract translation: 一种用于制造硅基MEMS压力传感器的方法包括：在具有第一和第二平行（100）表面的硅晶片的第一（100）表面中形成空腔，其中第一空腔的壁和第一（100） 它们与第一（100）表面相交的表面大于90度，并且腔体的底部和第二平行（100）表面之间的剩余材料包括柔性隔膜。 该方法还包括形成具有通孔的背衬晶片，并且将硅晶片结合到背衬晶片，使得背衬晶片中的孔与（100）硅晶片的第二侧中的空腔匹配。 在（100）硅晶片的第二侧上形成介电层，并且在介电层上形成感测元件以检测硅膜的压力引起的偏转。

公开(公告)号：EP3060290A1

公开(公告)日：2016-08-31

申请号：EP14803185.9

申请日：2014-10-15

Applicant: Swansea University

Inventor： LUI, Yufei ,  GUY, Owen

IPC: A61M37/00 ,  B81C1/00

CPC classification number: B81C1/00111 ,  A61M37/0015 ,  A61M2037/003 ,  A61M2037/0053 ,  B81B2201/055 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0159 ,  B81C2201/0176 ,  B81C2201/0181 ,  C23C16/402

Abstract: A method of forming microneedles where through a series of coating and etching processes microneedles are formed from a surface as an array. The microneedles have a bevelled end and bore which are formed as part of the process with no need to use a post manufacturing process to finish the microneedle.

公开(公告)号：EP2924000A4

公开(公告)日：2016-07-06

申请号：EP13857651

申请日：2013-11-01

Applicant: BEIJING NMC CO LTD

Inventor： JIANG ZHONGWEI

IPC: B81C1/00

CPC classification number: H01L21/32137 ,  B81C1/00531 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655