公开(公告)号：US20240314940A1

公开(公告)日：2024-09-19

申请号：US18604301

申请日：2024-03-13

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Ki Wook LEE ,  Chien Jen WANG

IPC: H05K3/42 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/429 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2203/107

Abstract: According to certain aspects, devices and methods can be provided for forming packaging substrates having ringless vias. For instance, a method of forming one or more vias in a packaging substrate can include: laminating a plurality of layers of a packaging substrate; drilling a via hole through the plurality of layers using a through drill, the plurality of layers not including a capture pad or ring along a path of the through drill for drilling the via hole; and forming a via in the via hole using a plating process.

公开(公告)号：US20240023227A1

公开(公告)日：2024-01-18

申请号：US17864396

申请日：2022-07-14

Applicant: FIRST HI-TEC ENTERPRISE Co., Ltd.

Inventor： Ching-Shan CHANG ,  Kun-Tao TANG ,  Tsung-Ting TSAI ,  Chien-Lin CHEN

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0228 ,  H05K1/111 ,  H05K2201/09236 ,  H05K2201/09545 ,  H05K2201/09718

Abstract: A circuit board comprises a substrate with opposite first and second sides. A pair of plated through holes (PTHs) extends along z-axis. A pair of signal traces are made on the first side of the substrate and electrically coupled to the pair of the PTHs respectively to form a differential pair. A ground metal is made on the second side of the substrate, the ground metal has a clearance made therein. The ground metal extends fully overlapping with the full signal traces to eliminate reflection noise caused by a boundary between the clearance and the metal ground.

公开(公告)号：US11751339B2

公开(公告)日：2023-09-05

申请号：US17449032

申请日：2021-09-27

Applicant: GLOBAL MASTER TECH. CO., LTD.

Inventor： Yao-Hua Kao ,  Chieh-Chien Chen

IPC: H05K1/02 ,  H05K3/34 ,  H05K1/11 ,  B23K1/00 ,  B23K101/42

CPC classification number: H05K3/3447 ,  B23K1/0016 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/115 ,  B23K2101/42 ,  H05K2201/096 ,  H05K2201/09545 ,  H05K2201/10704

Abstract: An electronic-component carrier board includes carrier plates formed in a stack, and insulating layers each disposed between two adjacent ones of the carrier plates. Multiple conductive pins extend through the insulating layers and the carrier plates. Multiple conductive wires equal in length and width are provided. Each conductive wire is connected to one of the conductive pins, covered by one of the insulating layers, disposed between two adjacent ones of the carrier plates, and extends outwardly from the stack of the carrier plates. A wiring method for the electronic-component carrier board is also disclosed.

公开(公告)号：US20230199957A1

公开(公告)日：2023-06-22

申请号：US17906853

申请日：2020-07-24

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Yejie HONG

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/18 ,  H05K3/46

CPC classification number: H05K1/115 ,  H05K3/0047 ,  H05K3/0076 ,  H05K3/188 ,  H05K3/4658 ,  H05K2201/096 ,  H05K2201/09545 ,  H05K2203/061 ,  H05K2203/0723 ,  H05K2203/167

Abstract: A multilayer substrate and a manufacturing method thereof are disclosed. The multilayer substrate includes two or more dielectric layers laminated in sequence; a public line disposed at a top or bottom dielectric layer of the two or more dielectric layers; and two or more first through hole pillars respectively each embedded in a respective one of the dielectric layers, and the first through hole pillars are connected in cascade and then connected with the public line.

公开(公告)号：US20180177049A1

公开(公告)日：2018-06-21

申请号：US15380054

申请日：2016-12-15

Applicant: NXP USA, INC.

Inventor： Michael B. Vincent ,  Zhiwei Gong ,  Scott M. Hayes

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/00 ,  H05K3/28 ,  H05K3/34 ,  H05K1/18 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49838 ,  H05K1/145 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3436 ,  H05K3/42 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/1178 ,  H05K2203/1316 ,  H05K2203/1327 ,  Y10T29/49165

Abstract: A plated hole with a sidewall plating. The plated hole has a vent opening that has a sidewall of non-conductive material that is not plated. During attachment of a joint conductive material such as solder to the sidewall plating, gasses generated from the attachment process are outgassed through the vent opening.

公开(公告)号：US09930791B2

公开(公告)日：2018-03-27

申请号：US14878096

申请日：2015-10-08

Applicant: IBIDEN CO., LTD.

Inventor： Mitsuhiro Tomikawa ,  Kota Noda ,  Nobuhisa Kuroda ,  Haruhiko Morita

IPC: H05K1/16 ,  H05K3/46 ,  H01G4/30 ,  H01G4/12 ,  H01G4/232 ,  H05K1/11 ,  H05K3/42 ,  H01L23/31 ,  H01G2/06

CPC classification number: H05K3/4697 ,  H01G2/06 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H01L23/3128 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2225/1058 ,  H01L2924/15331 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09545 ,  H05K2201/09827 ,  H05K2201/10015

Abstract: A wiring board with a built-in electronic component includes a substrate having a cavity, an interlayer insulating layer formed on the substrate such that the interlayer insulating layer is covering the cavity of the substrate, a conductor layer formed on the interlayer insulating layer, an electronic component accommodated in the cavity of the substrate and including a rectangular cuboid body and three terminal electrodes such that each of the three terminal electrodes has a metal film form formed on an outer surface of the rectangular cuboid body, and via conductors formed in the interlayer insulating layer such that the via conductors are connecting the conductor layer and the three terminal electrodes of the electronic component. The three terminal electrodes are arrayed in parallel on the outer surface of the rectangular cuboid body such that adjacent terminal electrodes have the opposite polarities.

公开(公告)号：US20180084652A1

公开(公告)日：2018-03-22

申请号：US15819289

申请日：2017-11-21

Applicant: International Business Machines Corporation

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Phillip V. Mann ,  Kevin M. O'Connell

IPC: H05K3/42 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/42 ,  H05K1/0216 ,  H05K1/11 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/09218 ,  H05K2201/09545 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a via plug with a specialized geometry and including a capillary is inserted into each via to allow electroplating on only preferred wall surfaces of the vias. Then a board plating process of the PCB manufacturing is performed.

公开(公告)号：US20170372994A1

公开(公告)日：2017-12-28

申请号：US15700483

申请日：2017-09-11

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48

CPC classification number: H05K1/0306 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3731 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/09 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0323

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

公开(公告)号：US09807867B2

公开(公告)日：2017-10-31

申请号：US15016147

申请日：2016-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jiun-Yi Wu ,  Chien-Hsun Lee ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H05K3/00 ,  H05K3/42 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/552 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4007 ,  H05K3/42 ,  H05K3/423 ,  H05K2201/0723 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2201/09645

Abstract: A method for manufacturing an interconnect structure and an interconnect structure are provided. The method includes: forming an opening in a substrate; forming a low-k dielectric block in the opening; forming at least one via in the low-k dielectric block; and forming a conductor in the via. The interconnect structure includes a substrate, a dielectric block, and a conductor. The substrate has an opening therein. The dielectric block is present in the opening of the substrate. The dielectric block has at least one via therein. The dielectric block has a dielectric constant smaller than that of the substrate. The conductor is present in the via of the dielectric block.

公开(公告)号：US20170273174A1

公开(公告)日：2017-09-21

申请号：US15245202

申请日：2016-08-24

Applicant: Industrial Technology Research Institute ,  First Hi-tec Enterprise Co.,Ltd. ,  NEXCOM International Co., Ltd.

Inventor： Chien-Min Hsu ,  Min-Lin Lee ,  Huey-Ru Chang ,  Hung-I Liu ,  Ching-shan Chang

IPC: H05K1/02 ,  H01P3/08 ,  H05K1/11

CPC classification number: H05K1/0245 ,  H01P3/08 ,  H05K1/0251 ,  H05K1/111 ,  H05K1/115 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09618 ,  H05K2201/09627

Abstract: A multi-layer circuit structure includes a differential transmission line pair and at least one conductive pattern. The differential transmission line pair includes first and second transmission lines disposed side by side. Each of the first and second transmission lines includes first and second segments connected to each other. An spacing between the two first segments is non-fixed, and an spacing between the two second segments is fixed. A first zone is located between the two first segments, a second zone is opposite to the first zone and located outside the first segment of the first transmission line, and a third zone is opposite to the first zone and located outside the first segment of the second transmission line. The conductive pattern is coplanar with the differential transmission line pair and disposed on at least one of the first, second and third zones. The conductive pattern is electrically connected to a reference potential and electrically insulated from the differential transmission line pair.