公开(公告)号：IL285001D0

公开(公告)日：2021-09-30

申请号：IL28500121

申请日：2021-07-20

Applicant: ADVANCED RISC MACH LTD ,  CRASKE SIMON JOHN ,  EAPEN JACOB

Inventor： CRASKE SIMON JOHN ,  EAPEN JACOB

IPC: G06F12/1036 ,  G06F12/14 ,  G06F21/71 ,  G06F21/85

Abstract: There is provided an apparatus comprising input circuitry that receives requests comprising input addresses in an input domain. Output circuitry provides output addresses. The output addresses comprise secure physical addresses to secure storage circuitry and non-secure physical addresses to non-secure storage circuitry. Lookup circuitry stores a plurality of mappings comprising at least one mapping between the input addresses and the secure physical addresses, and at least one mapping between the input addresses and the non-secure physical addresses.

公开(公告)号：IL255644A

公开(公告)日：2021-08-31

申请号：IL25564417

申请日：2017-11-14

Applicant: ADVANCED RISC MACH LTD

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/14

Abstract: A data processing apparatus comprises processing circuitry to execute a plurality of processes. An ownership table comprises one or more entries each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. A new process may be prevented from becoming an owner process until after successful completion of destructive overwriting. Ownership protection circuitry may detect a mismatch between an expected attribute, which is dependent on information in a page table entry, and an attribute specified in the ownership table. Each entry in the ownership table, for example, may indicate a level of encryption to be applied. Access control circuitry such as a memory management unit (MMU) may also determine whether an access request satisfies access permissions. The ownership table may also specify whether a higher privilege level process is allowed to access a block of physical addresses. A descriptor table may be used to store process state identifiers, where the process states may include invalid, prepare and execute states. The processes may comprise a hypervisor and/or a virtual machine (VM).

公开(公告)号：SG11202008479SA

公开(公告)日：2020-10-29

申请号：SG11202008479S

申请日：2019-01-25

Applicant: QUALCOMM INC

Inventor： BREHOVE JAMES ,  RAVEENDRAN VIJAYALAKSHMI ,  HAUGAN OLAV ,  BIGELOW BRITTON KENDALL ,  PARYANI KAVITA

IPC: G06F12/1036 ,  G06F9/455 ,  G06F12/1081 ,  G06F12/14

Abstract: Various embodiments include methods and devices for implementing secure peripheral interface disablement on a computing device. Various embodiments may include receiving a trigger to disable a peripheral interface associated with a peripheral device of the computing device, identifying a physical address of the peripheral interface, and securely removing a mapping of an intermediate physical address of the peripheral interface to the physical address of the peripheral interface.

公开(公告)号：GB2563879A

公开(公告)日：2019-01-02

申请号：GB201710338

申请日：2017-06-28

Applicant: ADVANCED RISC MACH LTD

Inventor： MATTHEW LUCIEN EVANS ,  GARETH RHYS STOCKWELL ,  JASON PARKER ,  MARTIN WEIDMANN

IPC: G06F12/14 ,  G06F12/1036

Abstract: A data processing system has a translation cache or translation look-aside buffer (TLB) 100 to store translations from virtual memory addresses to physical memory addresses. Each entry includes a translation context identifier 254 and a realm identifier 270. The translation context identifier may be virtual machine identifier 250 and an address space identifier 252. The realm corresponds to at least a portion of a process. When the system looks up a virtual memory address in the cache, the realm identifier and translation context identifier in the memory access request are compared with those in the translation cache entries. If both identifiers and the virtual memory address tag 262 match those in the entry, a match is found. In addition, if there is no match, a translation for the requested address is not added to the cache if the requesting realm is not permitted to access the address. The realm may also be matched if a visibility attribute indicates that the requesting realm is allowed to access the translation entry.

公开(公告)号：BR112017025619A2

公开(公告)日：2018-08-07

申请号：BR112017025619

申请日：2016-04-29

Applicant: QUALCOMM INC

Inventor： ALEXANDER MIRETSKI ,  BOHUSLAV RYCHLIK ,  CARLOS JAVIER MOREIRA ,  JASON EDWARD PODAIMA ,  KYLE JOHN ERNEWEIN ,  PAUL CHRISTOPHER JOHN WIERCIENSKI ,  SERAG MONIER GADELRAB

IPC: G06F12/1036 ,  G06F12/109

Abstract: trata-se do fornecimento de caches de tradução particionados de unidade de gerenciamento de memória (mmu), e aparelhos, métodos e mídias legíveis por computador relacionados. nesse sentido, em um aspecto, proporciona-se um aparelho que compreende uma mmu. a mmu compreende um cache de tradução que proporciona uma pluralidade de entradas de cache de tradução definindo mapeamentos de tradução de endereço. a mmu compreende, ainda, uma tabela de descritor de partição que proporciona uma pluralidade de descritores de partição definindo uma pluralidade de partições correspondentes que compreendem uma ou mais entradas de cache de tradução dentre a pluralidade de entradas de cache de tradução. a mmu também compreende um circuito de tradução de partição configurado para receber uma solicitação de acesso de memória a partir de um solicitante. o circuito de tradução de partição é configurado, ainda, para determinar um identificador de partição de cache de tradução (tcpid) da solicitação de acesso de memória, identificar uma ou mais partições dentre a pluralidade de partições com base no tcpid e realizar a solicitação de acesso de memória em uma entrada de cache de tradução de uma ou mais partições.

公开(公告)号：DE112016002006T5

公开(公告)日：2018-03-01

申请号：DE112016002006

申请日：2016-06-24

Applicant: GOOGLE LLC

Inventor： SEREBRIN BENJAMIN C

IPC: G06F12/1027 ,  G06F12/0813 ,  G06F12/1036 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/14 ,  G06F13/38 ,  G06F13/40

Abstract: Verfahren, Systeme und Vorrichtung, einschließlich auf einem Computerspeichermedium codierter Computerprogramme, für die Speicherung einer Adresse in einem Speicher eines Switches. Eines der Systeme beinhaltet einen Switch, der Pakete von Geräten empfängt und ihnen liefert, die mit einem Bus ohne Komponenten im Bus zwischen dem Switch und dem jeweiligen Gerät verbunden sind, wobei ein Speicher im Switch integriert ist, der eine Zuordnung virtueller Adressen zu physischen Adressen speichert, und ein Speichermedium im Switch integriert ist, das Anweisungen speichert, die vom Switch ausführbar sind. Diese veranlassen den Switch, Vorgänge durchzuführen, einschließlich des Empfangens einer Antwort auf eine Adressübersetzungsanforderung für ein Gerät, das durch den Bus mit dem Switch verbunden ist, wobei die Antwort eine Zuordnung einer virtuellen Adresse zu einer physischen Adresse beinhaltet, und Speicherung der Zuordnung der virtuellen Adresse zur physischen Adresse im Speicher als Reaktion auf das Empfangen der Antwort.

公开(公告)号：AU2016270028A1

公开(公告)日：2017-11-09

申请号：AU2016270028

申请日：2016-04-29

Applicant: QUALCOMM INC

Inventor： RYCHLIK BOHUSLAV ,  MOREIRA CARLOS JAVIER ,  GADELRAB SERAG MONIER ,  WIERCIENSKI PAUL CHRISTOPHER JOHN ,  MIRETSKY ALEXANDER ,  ERNEWEIN KYLE JOHN ,  PODAIMA JASON EDWARD

IPC: G06F12/1036 ,  G06F12/109

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, in one aspect, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

公开(公告)号：BRPI0925055A2

公开(公告)日：2015-07-28

申请号：BRPI0925055

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/06 ,  G06F9/44 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/00 ,  G06F15/00

公开(公告)号：DE112009005006T5

公开(公告)日：2013-01-10

申请号：DE112009005006

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  WANG LANDY ,  YAMADA KOICHI

IPC: G06F9/06 ,  G06F9/44 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/00 ,  G06F15/00

Abstract: Ein Verfahren und eine Vorrichtung zum Optimieren eines unbounded transactional memory (UTM) Systems werden hierin beschrieben. Eine Hardware-Unterstützung für Monitore, Puffer und Metadaten wird bereitgestellt, wobei orthogonale metaphysikalische Adressräume für Metadaten getrennt mit Threads und/oder Software-Untersystemen innerhalb von Threads verbunden werden können. Zusätzlich können die Metadaten durch Hardware in einer komprimierten Weise hinsichtlich für Software transparenten Daten gehalten werden. Darüber hinaus ist die Hardware in Reaktion auf eine Metadatenzugriffsinstruktion/Operationen in der Lage, einen erzwungenen Metadatenwert zu unterstützen, um mehrere Modi einer transaktionalen Ausführung freizugeben. Falls jedoch Monitore, gepufferte Daten, Metadaten oder andere Informationen verlorengehen oder Konflikte erfasst werden, sorgt die Hardware für Variationen einer Verlustinstruktion, die in der Lage ist, ein Transaktionsstaturregister für einen derartigen Verlust oder Konflikt zu pollen und die Ausführung zu einer Marke in Reaktion auf das Erfassen des Verlustes oder Konflikts zu springen. In ähnlicher Weise werden mehrere Variationen einer Commit-Instruktion bereitgestellt, um es Software zu ermöglichen, Commit-Bedingungen und Informationen zum Löschen bei einem Commit zu definieren. Darüber hinaus liefert die Hardware eine Unterstützung, um eine Aussetzung und Wiederaufnahme von Transaktionen bei Ringniveauübergängen zu ermöglichen.

公开(公告)号：GB201004294D0

公开(公告)日：2010-04-28

申请号：GB201004294

申请日：2010-03-15

Applicant: ADVANCED RISC MACH LTD

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036