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    ROBUST HIGH ASPECT RATIO SEMICONDUCTOR DEVICE
    241.
    发明公开
    ROBUST HIGH ASPECT RATIO SEMICONDUCTOR DEVICE 有权
    稳健半导体元件宽高比HIGH

    公开(公告)号：EP2334589A1

    公开(公告)日：2011-06-22

    申请号：EP09787279.0

    申请日：2009-09-24

    Applicant: NXP B.V.

    Inventor： ROOZEBOOM, Freddy ,  GOOSSENS, Martijn ,  BESLING, Willem Frederik Adrianus ,  VERHAEGH, Nynke

    IPC: B81B1/00 ,  B81C99/00 ,  H01L29/41 ,  H01L31/0224

    CPC classification number: H01L29/41 ,  B81B3/007 ,  B81B2201/06 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L28/91

    Abstract: The invention relates to an semiconductor device comprising a first surface and neighboring first and second electric elements arranged on the first surface, in which each of the first and second elements extends from the first surface in a first direction, the first element having a cross section substantially perpendicular to the first direction and a sidewall surface extending at least partially in the first direction, wherein the sidewall surface comprises a first section and a second section adjoining the first section along a line extending substantially parallel to the first direction, wherein the first and second sections are placed at an angle with respect to each other for providing an inner corner wherein the sidewall surface at the inner corner is, at least partially, arranged at a constant distance R from a facing part of the second element for providing a mechanical reinforcement structure at the inner corner.

    VERFAHREN ZUM PLASMAÄTZEN ZUR ERZEUGUNG POSITIVER ÄTZPROFILE IN SILIZIUMSUBSTRATEN
    243.
    发明授权
    VERFAHREN ZUM PLASMAÄTZEN ZUR ERZEUGUNG POSITIVER ÄTZPROFILE IN SILIZIUMSUBSTRATEN 有权
    用于生产等离子体刻蚀阳性硅衬底

    公开(公告)号：EP2084734B1

    公开(公告)日：2011-05-11

    申请号：EP07785710.0

    申请日：2007-08-15

    Applicant: Technische Universität Dresden

    Inventor： RICHTER, Karola ,  ZSCHÄTZSCH, Gerd

    IPC: H01L21/3065 ,  B81C1/00

    CPC classification number: H01L21/30655 ,  B81C1/00626 ,  B81C99/009 ,  B81C2201/0132

    Abstract: The invention relates to a plasma etching method for producing positive etching profiles (4) in silicon substrates (1) whose features (11), etched using a mask (2), have a feature overhang (5) at the edge in the region of the feature entrance opening (8), said feature overhang being oriented toward the centre of the feature entrance opening (8), where a first etching operation is performed using first isotropic etching and using first anisotropic etching in a first time ratio (Z1). The object is to remove the feature overhangs which are produced when etching using masks and which are produced directly beneath the mask in the surface region of the treated patterned silicon substrates. The object is achieved by removing the feature overhang (5) by performing a maskless second etching operation with the following steps: A) second anisotropic etching of the silicon substrate (1) which has the feature overhang, with a polymer layer being produced on the side walls (3), B) removal of the polymer layer from the side walls (3) using an O2 plasma, C) second isotropic etching of the silicon substrate (1), with the second etching operation being performed using a second time ratio (Z2) on the basis of equation (II), linked to a change of etching profile which is free of any feature overhang, until at least one feature entrance angle (α), where α = 0°, is achieved in the region of the feature entrance opening (8), the period of time (tisotrop - 2) for the second isotropic etching and the period of time (tanisotrop - 2 ) for the second anisotropic etching being prescribed.

    A method to create narrow trenches in dielectric materials
    245.
    发明公开
    A method to create narrow trenches in dielectric materials 有权
    一种用于在所述的介电材料制造窄沟槽方法

    公开(公告)号：EP1764830A3

    公开(公告)日：2009-02-18

    申请号：EP05447238.6

    申请日：2005-10-21

    Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM ( IMEC)

    Inventor： Beyer, Gerald

    IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311

    CPC classification number: H01L21/31111 ,  B81C1/00595 ,  B81C2201/0132 ,  B81C2201/0133 ,  H01L21/31633 ,  H01L21/76224 ,  H01L21/76816

    Abstract: The present invention relates to a method for the production of very small trenches in semiconductor devices.
    The formation of these small trenches is based on chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in said first dielectric layer are converted locally and become etchable by a first etching substance. Subsequently a second dielectric material is deposited in the patterned structure and the damaged part of the first dielectric material is removed such that small trenches are obtained.
    The small trenches obtained by chemically changing the properties of a dielectric layer can be used as test vehicle to study barrier deposition, copper plating and seedlayer deposition within very small trenches (order 10-30 nm).

    High resolution plasma etch
    246.
    发明公开
    High resolution plasma etch 审中-公开
    HochauflösendePlasmaätzung

    公开(公告)号：EP2006249A2

    公开(公告)日：2008-12-24

    申请号：EP08158646.3

    申请日：2008-06-20

    Applicant: FEI COMPANY

    Inventor： Toth, Milos ,  Smith, Noel

    IPC: B81C1/00

    CPC classification number: B05C21/005 ,  B81C1/00531 ,  B81C2201/0132 ,  B81C2201/0143 ,  H01J37/3053 ,  H01J37/317 ,  H01J2237/3174 ,  H01J2237/31744 ,  H01J2237/31749

    Abstract: A method for fabrication of microscopic structures that uses a beam process, such as beam-induced decomposition of a precursor, to deposit a mask in a precise pattern and then a selective, plasma beam is applied, comprising the steps of first creating a protective mask upon surface portions of a substrate using a beam process such as an electron beam, focused ion beam (FIB), or laser process, and secondly etching unmasked substrate portions using a selective plasma beam etch process. Optionally, a third step comprising the removal of the protective mask may be performed with a second, materially oppositely selective plasma beam process.

    Abstract translation: 应用一种制造微结构的方法，该方法使用光束过程，例如光束诱导的前体分解，以精确图案沉积掩模，然后选择性等离子束，包括以下步骤：首先产生保护掩模 使用诸如电子束，聚焦离子束（FIB）或激光工艺的光束过程在衬底的表面部分上，并且使用选择性等离子体束蚀刻工艺二次蚀刻未掩模的衬底部分。 可选地，包括去除保护掩模的第三步骤可以用第二种，实质上相对选择的等离子体束工艺进行。

    Endpoint detection in time division multiplexed processes using an envelope follower algorithm
    247.
    发明授权
    Endpoint detection in time division multiplexed processes using an envelope follower algorithm 有权
    终点检测在时分方法使用Hüllkurvenalgorithmus

    公开(公告)号：EP1623457B1

    公开(公告)日：2008-11-26

    申请号：EP04751610.9

    申请日：2004-05-06

    Applicant: Unaxis USA Inc.

    Inventor： WESTERMAN, Russell ,  JOHNSON, David

    IPC: H01L21/66

    CPC classification number: H01J37/32935 ,  B81C1/00587 ,  B81C2201/0132 ,  H01J37/32963 ,  H01L21/30655

    Abstract: The present invention provides a method for establishing endpoint during an alternating cyclical etch process or time division multiplexed process. A substrate is placed within a plasma chamber and subjected to an alternating cyclical process having an etching step and a deposition step. A variation in plasma emission intensity is monitored using known optical emission spectrometry techniques. An amplitude information is extracted from a complex waveform of the plasma emission intensity using an envelope follower algorithm. The alternating cyclical process is discontinued when endpoint is reached at a time that is based on the monitoring step.

    Method for manufacturing a micro-electro-mechanical structure
    249.
    发明公开
    Method for manufacturing a micro-electro-mechanical structure 有权
    Verfahren zum Herstellen einer mikroelectromechanischen Struktur

    公开(公告)号：EP1770056A2

    公开(公告)日：2007-04-04

    申请号：EP06076692.0

    申请日：2006-09-07

    Applicant: Delphi Technologies, Inc.

    Inventor： Chilcott, Dan W.

    IPC: B81B3/00 ,  B81C1/00

    CPC classification number: B81C1/00531 ,  B81B2203/033 ,  B81C2201/0132 ,  B81C2201/0142

    Abstract: A technique (500) for manufacturing a micro-electro-mechanical (MEM) structure includes a number of steps. Initially, a substrate is provided (502). Next, a plurality of trenches are etched into the substrate with a first etch (508). Then, a charging layer is formed at a bottom of each of the trenches to form undercut trenches (510). Finally, a second etch is provided into the undercut trenches. The charging layer causes the second etch to laterally etch foots in the substrate between the undercut trenches (512). The footers undercut the substrate to release a portion of the substrate for providing a movable structure between the undercut trenches and above the footers.

    Abstract translation: 用于制造微机电（MEM）结构的技术（500）包括多个步骤。 首先，提供基板（502）。 接下来，通过第一蚀刻（508）将多个沟槽蚀刻到衬底中。 然后，在每个沟槽的底部形成充电层以形成底切槽（510）。 最后，在底切沟槽中提供第二蚀刻。 充电层使得第二蚀刻在底切沟槽（512）之间横向蚀刻衬底中的脚。 底脚底切基板以释放基板的一部分，以在底切沟槽和页脚之上提供可移动结构。

    Method of making a soi silicon structure
    250.
    发明公开
    Method of making a soi silicon structure 审中-公开
    Verfahren zum Herstellen einer SOI-Struktur

    公开(公告)号：EP1734000A2

    公开(公告)日：2006-12-20

    申请号：EP06076128.5

    申请日：2006-05-30

    Applicant: Delphi Technologies, Inc.

    Inventor： Chilcott, Dan W.

    IPC: B81C1/00

    CPC classification number: B81C1/00944 ,  B81C2201/0132

    Abstract: A process for making a microelectromechanical device having a moveable component defined by a gap pattern in a semiconductor layer of a silicon-on-insulator wafer (10) involves the use of a plurality of deep reactive ion etching steps at various etch depths that are used to allow a buried oxide layer (14) of the silicon-on-insulator wafer (10) to be exposed in selected areas before the entire moveable component of the resulting device is freed for movement. This method allows wet release techniques to be used to remove the buried oxide layer (14) without developing stiction problems. This is achieved by utilizing deep reactive ion etching to free the moveable component after a selected portion of the buried oxide layer (14) has been removed by wet etching.

    Abstract translation: 一种用于制造具有由绝缘体上硅晶片（10）的半导体层中的间隙图案限定的可移动部件的微机电装置的方法涉及使用多个深反应离子蚀刻步骤，所述深反应离子蚀刻步骤在使用的各种蚀刻深度 允许绝缘体上硅晶片（10）的掩埋氧化物层（14）在所得到的器件的整个可移动部件被释放以便移动之前暴露在选定的区域中。 该方法允许湿式释放技术用于去除埋入氧化物层（14）而不产生粘性问题。 这是通过利用深反应离子蚀刻在通过湿法蚀刻去除掩埋氧化物层（14）的选定部分之后释放可移动部件来实现的。

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