公开(公告)号：JPH05136017A

公开(公告)日：1993-06-01

申请号：JP12345692

申请日：1992-05-15

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SAN UON KAN ,  KIYON SOO RII

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/76 ,  H01L21/8252 ,  H01L29/84

Abstract: PURPOSE: To reduce interface stress that is generated between substrates, due to the difference in thermal coefficient of expansion at the time of heat treatment by forming a plurality of grooves vertically and horizontally, forming a second low-temperature silicon oxide film at the sidewall of the grooves, and performing the adhesion thermal treatment to a single-crystal silicon for a polycrystalline silicon film. CONSTITUTION: A compound semiconductor layer 2 and a compound semiconductor layer 3 for forming an element are subjected to epitaxial growth on a compound semiconductor substrate 1. A low-temperature silicon oxide film 4 and a polycrystalline silicon oxide film 5 are successively laminated on the compound semiconductor layer 3 for forming an element, and a groove 6 reaching the compound semiconductor substrate 1 is formed vertically and horizontally. The sidewall of the groove 6 is covered with a low-temperature silicon oxide film 7a, and adhesion heat treatment is performed to the polycrystalline silicon film 5 and a single-crystal silicon substrate 8. In this case, a space formed inside the groove absorbs a stress that is generated, due to the difference in thermal coefficients of expansion between the compound semiconductor substrate the compound semiconductor layer, and the single-crystal silicon substrate.

公开(公告)号：JPH03180066A

公开(公告)日：1991-08-06

申请号：JP22953590

申请日：1990-08-29

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI KIKOU ,  KIN DAIYOU ,  RI CHINKOU ,  KIN SENJIYU

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To enlarge the area of a storage capacitor by depositing n polysilicon on a dielectric layer while coupling with an n diffused layer around a trench and on the bottom thereof thereby forming a plate. CONSTITUTION: After forming a primary dielectric layer 43a for capacitor in a trench, n doped polysilicon is deposited to form a secondary dielectric layer 43b. Subsequently, polysilicon is deposited thereon continuously to an n diffused layer around a trench and on the bottom thereof thus forming a plate 45. Since the capacitor between a polysilicon storage electrode 41 and the n diffusion plate 45, as well as the capacitor between the n polysilicon storage electrode 41 and the n diffused plate 45, can be utilized entirely as a storage capacitor, surface efficiency of the storage capacitor can be enhanced.

公开(公告)号：JPH03128562A

公开(公告)日：1991-05-31

申请号：JP5824690

申请日：1990-03-12

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： KUON KUU RII ,  JIN YAN CHIYOI ,  YAN SOO CHIYO ,  HIEN HOO RII

IPC: H04M3/22 ,  H04J3/12 ,  H04L12/70 ,  H04L29/02 ,  H04M3/36 ,  H04M7/06 ,  H04Q1/30 ,  H04Q3/00 ,  H04Q3/545 ,  H04Q3/66

Abstract: PURPOSE: To maintain the load balance of a message communication processing processor (MHP) by almost equally re-allocating plural message processing selection codes (MHSC) assigned to a defective MHP to each available MHP when any MHP breaks down. CONSTITUTION: When failure is generated in the node (interrupted point) of an MHP or the related link (signal line) of the MHP, the number of the active MHP is number-changed to the virtual number (virtual number, VMHP) of the MHP, and a take-over procedure is started based on the quotient of MHSC /N-i. For example, a signal message having a quotient 0 is path-designated to a VMHP#0, a signal message having a quotient 1 is path-designated to a VMHP#1, a signal message having a quotient (j) is path-designated to a VMHP#, and a signal message having a quotient (N-i-1) is path-designated to a VMHP#(N-i-1). In this case, when the number of the available MHP is equal to (N-i), and the quotient is larger than (N-i), this quotient is changed to (N-i), and the path designation of the message is executed.

公开(公告)号：JPH03121898A

公开(公告)日：1991-05-23

申请号：JP15563190

申请日：1990-06-15

Applicant: KOREA ELECTRONICS TELECOMM ,  YUSHIN ELECTRON CO LTD ,  GOLD STAR CO

Inventor： I YURU RII ,  UN SUN YU ,  SHIN UKU PAKU ,  CHIYUN HAKU YAN

IPC: B42D15/10 ,  C09D5/23 ,  G06K19/06 ,  G06K19/10 ,  G06K19/12 ,  G11B5/80

Abstract: PURPOSE: To identify a forgery by doubling a magnetic recording layer, using one layer as recording and reproducing a signal, using the other for giving a specific pattern, giving changes in an angle, interval and thickness, and changing a residual magnetic flux density. CONSTITUTION: The magnetic card 14 completed by adding the same magnetic material as a first magnetic material on a base film 13 completed for painting with first magnetic material paint, and forming a second magnetic material paint lay er having a pattern of specific angle, interval and thickness by using rollers 11, 12. At this time, the pattern, frequency, induced voltage and the like of the card are decided according to characteristics of an oblique pattern, pattern interval, pattern thickness and the like via a twisting angle θ of the rollers 11, 12 to give intrinsicalness to the card, and hence a forgery can be identified.

公开(公告)号：JPH03117953A

公开(公告)日：1991-05-20

申请号：JP25498990

申请日：1990-09-25

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： YON FUI RI ,  YON SHIKU BEKU ,  SOKU GI RI ,  KUN U RI ,  CHIYON OKU CHIYAA

IPC: H04M3/22 ,  H04M7/06 ,  H04Q3/00

Abstract: PURPOSE: To improve the reliability of a system by making a level 3-3 connection network duplex for changing modules through the normal procedures as the time of the occurrence of a fault. CONSTITUTION: A signal relay system constituted mainly of the duplex level 3-3 connection network consists of level 3-3 connection networks 100a and 100b, a signal message processing module 110, a signal network management module 120, an O/M(operation and maintenance) system 130 and a terminal 140. Consequently, many level 2 units and modules 110 and 120 are not unavailable, namely available even if a fault occurs in one level 3-3 connection network. A time margin for maintenance of one route where a fault occurred and another route free from the occurrence of a fault are used to perform the maintenance. Thus, modules are changed through normal procedures.

公开(公告)号：JPH03104365A

公开(公告)日：1991-05-01

申请号：JP23343290

申请日：1990-09-05

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： JIE SABU RII ,  PIYUN HOO IE ,  MI SUKU HAN

IPC: H04M3/22 ,  G04G7/00 ,  G06F1/14 ,  H04Q3/545

Abstract: PURPOSE: To maintain high reliability at the time of managing the time of an electronic exchange system by periodically inspecting the coincidence of system time, inspecting the maximum and minimum ranges of time to be referred to at the time of system time management and inspecting the system itself about time information. CONSTITUTION: A time management system in an exchange is provided with a 1st step for registering a timer to be started at a prescribed interval and requesting and receiving hardware time from a network synchronization processor 6 to a realtime generating circuit 7, a 2nd step for mutually comparing system time and time information received by the 1st step and inspecting whether or not a difference of more than a prescribed time exists between both the time information and a 3rd step for maintaining current time as it is and requesting hardware time adjustment, based on the system time when the number of time points including no difference more than the prescribed time value is more than a prescribed value. However, when the contents of the time information are mutually different, the system time based on preferential hardware time is redetermined. Consequently, stable and consistent time can be provided to all processors 1 to 6 which require time information.

公开(公告)号：JPH0282629A

公开(公告)日：1990-03-23

申请号：JP31400288

申请日：1988-12-14

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SHIN KIYU FUAN ,  CHIYOE YONGU KIYU ,  YAN JIYON UTSUKU ,  I JIN HII ,  KAN JIN YONGU

IPC: H01L29/812 ,  H01L21/285 ,  H01L21/338 ,  H01L29/78

Abstract: PURPOSE: To form an N layer through a self-aligned method for contact of low resistance by a method wherein a multilayer photoresist prescribed in dimensional and formed through a photograph transfer technique is transferred as reduced to a specific scale through reactive ion etching, and a required gate plated with gold, T-shaped, and high in dimensional accuracy is formed taking advantage of side etching of a lower photoresist layer. CONSTITUTION: A temporary gate 111 is formed by etching through a reduction transfer method wherein a shape of size 0.6 to 1.0μm is transferred at a reduction ration 2:1. Titanium is evaporated on tungsten silicide, plating is carried out making the evaporated titanium serve as an electrode, plating is carried out at a growth rate of 0.1μm/min or so at a temperature of 50 deg.C taking advantage of the exposed titanium 104a as an electrode, whereby a specified T-shaped gate is formed. Taking advantage of a photograph transfer method, the shape of a transistor region which comprises source. drain regions is limited by a photoresist 105b, silicon ions are implanted at an ion dose of 1E13 to 5E13/cm with en energy of 100 to 200keV using the T-shaped gate as a mask, whereby a silicon ion-implanted layer 115 as an N layer is formed at the resistive joint of a source and a drain in a self-aligned manner.

公开(公告)号：JPH0262072A

公开(公告)日：1990-03-01

申请号：JP7367389

申请日：1989-03-24

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIMU KUWAN SUU ,  CHIE SAN FUN ,  KIMU IOFUAN ,  KIMU BOU ,  I JINHO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/70 ,  H01L29/732

Abstract: PURPOSE: To increase the degree of integration and operating speed of a composite semiconductor element, by mounting a bipolar element formed by minimizing the width of its inactive base region and a highly integrated CMOS element on one water in a mixing state. CONSTITUTION: After an N -buried layer 104 is formed on the surface 102 of a P -type silicon wafer substrate by diffusion, an N-type epitaxial layer 103 is grown and deposited by doping the layer 104 with phosphorus. Then, after a P -type junction separating area 106 is prescribed by utilizing a field mask, boron is injection into the area 106. After injection, an oxide film 107 is grown and the gates 111 of an NMOS element and a PMOS element and the emitter 112 and collector 113 of a bipolar transistor are fomred by anisotropic etching. Then, the sources/drains 116 of the PMOS and NMOS 117 elements are formed by implanting boron ions. Finally, an inactive base region and junctions are fomred so as to reduce the base serial resistance of the bipolar transistor.

公开(公告)号：JPH0247824A

公开(公告)日：1990-02-16

申请号：JP32957488

申请日：1988-12-28

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： I JIE SHIN ,  KAN JIN YON

IPC: C01B31/02 ,  G03F1/22 ,  H01L21/027 ,  H01L21/306 ,  H01L21/31

Abstract: PURPOSE: To improve the transmittivity, heat resistance and chemical stability for X-rays and visible rays by forming an amorphous C film by the plasma evaporation method on an Si or quartz glass wafer. CONSTITUTION: An amorphous C film 102 is formed by the plasma evaporation method on an Si or quartz glass wafer 101. On the back of the wafer 101 an insulation film 104 is deposited and partly etched to form a mask through which the wafer 101 is then wet etched with a KOH soln. On the film 102, an Au or W metal fiber 1205 is deposited, and a resist pattern 106 is formed thereon and etched to form an integrated circuit pattern, thus obtaining a homogeneous and wide thin film superior in transmittivity, heat resistance, chemical stability and strength for X-rays and visible rays by the plasma chemical vapor deposition. On the wafer 101 an aggregation compensating fiber 103 and amorphous C film 102 are laminated to compensate the compression aggregation of the C film and improve the strength and film thickness uniformity.

公开(公告)号：JPH01173736A

公开(公告)日：1989-07-10

申请号：JP19286388

申请日：1988-08-03

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI SOUSHIYU ,  KIYOU HOUKIYUU ,  BOKU KATSUNORI ,  YUU KEISHIYUN

IPC: H01L21/677 ,  B25J9/04 ,  B25J15/00 ,  H01L21/687

Abstract: PURPOSE: To make it possible to easily shift an wafer of a different diameter without replacing a device by forming an wafer supporting part having plural fixed pins on the front side of a machine arm and forming a constant pressure spring for energizing slide arm to the front side. CONSTITUTION: Fixed pins 41, 411 having respectively different height and a fixed pin 412 to be optionally depressed are arranged on the front end of the wafer supporting part 40 and an wafer of a maximum diameter is supported by the pin 41 and a balance pin 43. The slide arm 31 is arranged so as to be optionally slidden against the machine arm 30 and holds the center of the wafer on the center of the supporting part 40 in cooperation with one of the pins 41, 43, 411. 412. The constant pressure spring 53 is arranged on the rear side of the arm 30 so as to hold the wafer by energizing the arm 31 to the front side by fixed pressure. Consequently an wafer of a different diameter can be safely and accurately transferred in the coincident state of the wafer center with the arm center without replacing the machine arm.