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公开(公告)号：HRP20180982T1
公开(公告)日：2018-08-10
申请号：HRP20180982
申请日：2018-06-27
Applicant: IBM
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公开(公告)号：DK2769382T3
公开(公告)日：2018-07-16
申请号：DK12871181
申请日：2012-11-15
Applicant: IBM
Inventor： BRADBURY JONATHAN DAVID , GSCHWIND MICHAEL KARL , SCHWARZ ERIC MARK , SLEGEL TIMOTHY , JACOBI CHRISTIAN
IPC: G06F9/30
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公开(公告)号：ES2675512T3
公开(公告)日：2018-07-11
申请号：ES12871181
申请日：2012-11-15
Applicant: IBM
Inventor： BRADBURY JONATHAN , GSCHWIND MICHAEL , SCHWARZ ERIC , SLEGEL TIMOTHY , JACOBI CHRISTIAN
Abstract: Un producto de programa informático para ejecutar una instrucción de máquina en una unidad central de procesamiento, comprendiendo el producto de programa informático: un medio de almacenamiento legible con ordenador, legible por medio de un circuito de procesamiento, e instrucciones de almacenamiento para su ejecución por el circuito de procesamiento para llevar a cabo un método que comprende: obtener, mediante el procesador, una instrucción de máquina para su ejecución, estando la instrucción de máquina definida para su ejecución con ordenador conforme a una arquitectura de ordenador, comprendiendo la instrucción de máquina (300): al menos un campo de opcode (302a) para proporcionar un opcode; un campo de registro (304) para ser usado a efectos de designar un registro (R1), comprendiendo el registro un primer operando, y al menos un campo (306) para indicar una posición de un segundo operando, comprendiendo el segundo operando una dirección de inicio del bloque de memoria principal, y caracterizado porque el opcode identifica una operación de Conteo de Carga hasta Límite de Bloque, siendo la operación de Conteo de Carga hasta Límite de Bloque para calcular una distancia desde una posición en la memoria principal hasta un límite de un bloque de memoria principal, y porque el método comprende además ejecutar la instrucción de máquina para realizar la operación de Conteo de Carga hasta Límite de Bloque, comprendiendo la ejecución: determinar la distancia desde la posición del segundo operando hasta el límite del bloque de memoria principal, comprendiendo la determinación de la distancia contar mediante el procesador el número de bytes desde la posición del segundo operando hasta el límite del bloque de memoria, y disponer un valor que representa la distancia en el primer operando, siendo este valor un resultado de ejecutar la operación de Conteo de Carga hasta Límite de Bloque.
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公开(公告)号：CA3036118A1
公开(公告)日：2018-04-05
申请号：CA3036118
申请日：2017-09-27
Applicant: IBM
Inventor： GREINER DAN , SLEGEL TIMOTHY , ZOELLIN CHRISTIAN
Abstract: An instruction to be used to produce a message digest for a message is executed. In execution, a padding state control of the instruction is checked to determine whether padding has been performed for the message. If the checking indicates padding has been performed, a first action is performed; and if the checking indicates padding has not been performed, a second action, different from the first action, is performed.
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公开(公告)号：CA2786049C
公开(公告)日：2018-02-13
申请号：CA2786049
申请日：2010-11-08
Applicant: IBM
Inventor： GREINER DAN , MITRAN MARCEL , SLEGEL TIMOTHY
Abstract: A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed. In various embodiments, a high-word facility is utilized to determine selective access by different subsets of program instructions to a high order portion of the GPRs or to a low order portion of the GPRs. This functionality extends the number of GPRs available to sets of program instructions and relieves dependency on architectural resources, thereby improving software program functionality and performance.
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Patent Agency Ranking
公开(公告)号：AU2015238665B2
公开(公告)日：2018-01-18
申请号：AU2015238665
申请日：2015-03-16
Applicant: IBM
Inventor： GREINER DAN , FARRELL MARK , OSISEK DAMIAN LEO , SCHMIDT DONALD WILLIAM , BUSABA FADI YUSUF , KUBALA JEFFREY PAUL , BRADBURY JONATHAN DAVID , HELLER LISA CRANTON , SLEGEL TIMOTHY , GAINEY JR CHARLES
Abstract: A computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.
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公开(公告)号：CA2701086C
公开(公告)日：2017-09-19
申请号：CA2701086
申请日：2009-01-05
Applicant: IBM
Inventor： GREINER DAN , GAINEY JR CHARLES , HELLER LISA , OSISEK DAMIAN , SLEGEL TIMOTHY , SITTMANN III GUSTAV
IPC: G06F9/30 , G06F12/1009 , G06F12/14
Abstract: What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.
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公开(公告)号：AU2013375140B2
公开(公告)日：2017-03-23
申请号：AU2013375140
申请日：2013-12-06
Applicant: IBM
Inventor： BRADBURY JONATHAN DAVID , SCHWARZ ERIC MARK , SLEGEL TIMOTHY , GSCHWIND MICHAEL KARL
IPC: G06F17/16
Abstract: Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception.
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公开(公告)号：AU2015330266A1
公开(公告)日：2017-03-09
申请号：AU2015330266
申请日：2015-09-14
Applicant: IBM
Inventor： FARRELL MARK , HELLER LISA , KUBALA JEFFREY PAUL , SCHMIDT DONALD WILLIAM , GREINER DAN , SLEGEL TIMOTHY , BUSABA FADI YUSUF , OSISEK DAMIAN , BRADBURY JONATHAN DAVID , LEHNERT FRANK , NERZ BERND , JACOBI CHRISTIAN
Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.
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公开(公告)号：MX2016011905A
公开(公告)日：2016-12-02
申请号：MX2016011905
申请日：2015-03-11
Applicant: IBM
Inventor： SLEGEL TIMOTHY , SCHWARZ ERIC MARK , JACOBI CHRISTIAN , FADI YUSUF BUSABA , MICHAEL KARL GSCHWIND , VALENTINA SALAPURA , HAROLD WADE CAIN III
Abstract: Las modalidades se relacionan con la implementación de un protocolo de coherencia. Un aspecto incluye enviar una petición de datos a un procesador remoto y recibir por medio de un procesador una respuesta del procesador remoto. La respuesta tiene un estado de transición de una transacción remota en el procesador remoto. El procesador agrega el estado de transacción de la transacción remota en el procesador remoto en la tabla de seguimiento de interferencia de transacción local.
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