公开(公告)号：KR1020140002731A

公开(公告)日：2014-01-08

申请号：KR1020137021344

申请日：2012-01-13

Applicant: 카벤디시 키네틱스, 인크.

Inventor： 르노,미카엘 ,  레이시,조셉대미언고든 ,  조쉬,비크람 ,  맥과이어,토머스엘.

IPC: B81C1/00 ,  H01L29/84 ,  H01L21/00

CPC classification number: B81B3/0072 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2207/096 ,  B81C1/00039 ,  B81C1/00333 ,  B81C1/00476 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2203/0145 ,  B81C2203/0714

Abstract: 본 발명은 일반적으로 MEMS 또는 NEMS 디바이스를 제조하는 방법 및 이 디바이스에 관한 것이다. 캔틸레버 구조체에 비해 더 낮은 재결합 계수를 가지는 물질의 박막 층은 캔틸레버 구조체, RF 전극 및 풀오프 전극 위에 증착될 수 있다. 박막층은 공동으로 도입되는 에칭 가스로 하여금 공동 내에 전체 에칭제 재결합 속도를 감소시켜 공동 내에 희생 물질의 에칭 속도를 증가시킬 수 있게 한다. 에칭제 그 자체는 희생 물질의 최상부 층이 제일 먼저 에칭되도록 캔틸레버 구조체의 앵커 부분과 선형으로 정렬된 캡슐 층 내 개구를 통해 도입될 수 있다. 이후 밀봉 물질이 공동을 밀봉할 수 있고 이 밀봉 물질은 공동을 통해 앵커 부분으로 연장하여 앵커 부분에 추가적인 강도를 제공한다.

公开(公告)号：KR1020130103149A

公开(公告)日：2013-09-23

申请号：KR1020120024551

申请日：2012-03-09

Applicant: 주식회사 윈텔

Inventor： 정성현 ,  이향주

IPC: H01L21/3065

CPC classification number: B81C1/00531 ,  B81C1/00619 ,  B81C2201/0132 ,  H01J37/321 ,  H01J37/32174 ,  H01L21/30655 ,  H01L21/67069 ,  H01L21/76898

Abstract: PURPOSE: A plasma processing method and a substrate processing apparatus are provided to form a through silicon via hole with the uniformity of a large area and a fast processing speed. CONSTITUTION: A first plasma source (110a) and a second plasma source (210b) are mounted in a chamber (152). A first gas is provided to the first plasma source. A second gas is different from the first gas and is provided to the second plasma source. First plasma is formed by applying power to the first plasma source. Second plasma is formed by applying the power to the second plasma source. A substrate (156) is processed in the chamber by using the first plasma and the second plasma.

Abstract translation: 目的：提供等离子体处理方法和基板处理装置，以形成具有大面积均匀性和快速处理速度的贯穿硅通孔。 构成：将第一等离子体源（110a）和第二等离子体源（210b）安装在腔室（152）中。 第一气体被提供给第一等离子体源。 第二气体与第一气体不同，并且被提供给第二等离子体源。 通过对第一等离子体源施加电力来形成第一等离子体。 通过将电力施加到第二等离子体源来形成第二等离子体。 通过使用第一等离子体和第二等离子体在腔室中处理衬底（156）。

公开(公告)号：KR100593915B1

公开(公告)日：2006-06-30

申请号：KR1020040046014

申请日：2004-06-21

Applicant: 삼성전기주식회사

Inventor： 김종삼 ,  이성준 ,  이로운

IPC: B81B7/02

CPC classification number: B81C1/00936 ,  B81C2201/0132

Abstract: 본 발명은 멤스구조체및 이를 제조하는 방법에 관한 것으로, 상,하부실리콘층사이에 산화막이 개재된 웨이퍼기판과, 상기 웨이퍼기판에 일체로 연결되는 고정부및 상기 고정부에 대하여 유동가능하게 부유되는 가동부로 이루어지는 멤스구조체에 있어서, 상기 상부실리콘층에 1차 건식식각으로 형성되고, 2차 건식식각시 바닥면의 산화막이 제거된 에칭홀을 통해 통해 공급되는 식각용 가스에 의해 상기 가동부를 부유시키도록 일정깊이로 상기 하부실리콘층에 건식식각되는 부유공간과, 상기 부유공간을 사이에 두고 상기 하부실리콘층과 대응하도록 상기 가동부의 하부면에 잔류하는 쇼트방지용 산화막을 포함하여 구성된다.
본 발명에 의하면, 가동부의 움직임이 가능하도록 부유시키는 공간을 건식식각으로 형성하여 습식식각시 에칭액 건조과정에서 발생되던 점착현상을 근본적으로 방지하고, 전기적 특성및 안정성을 보장하며, 접착에 의한 쇼트사고를 미연에 방지할 수 있다.
멤스, 점착, 산화막, 웨이퍼기판, 에칭홀, 부유공간, 건식식각, 이온충격

公开(公告)号：KR1020060034849A

公开(公告)日：2006-04-26

申请号：KR1020040083855

申请日：2004-10-20

Applicant: 삼성전자주식회사

Inventor： 정석환 ,  최형

IPC: H01L21/20 ,  H01L27/12

CPC classification number: B81C1/00579 ,  B81C2201/0132

Abstract: 개시된 SOI(Silicon on Insulator)기판은 기판, 산화막층, 실리콘층이 차례로 적층되어 구성되며, 산화막층에는 통전홀이 형성되어 실리콘층의 일부가 통전홀을 통해 매립되어 기판과 연통된다. 따라서, 실리콘층 딥 에칭시 노치가 발생되는 것을 해소시킨다. 이러한 SOI기판 구조를 응용하여 부유 구조체를 제조함에 따라 부유 구조체의 식각성을 향상시킨다. 그 부유 구조체 제조 방법은 기판에 소정 두께로 산화막층을 형성하는 단계와, 산화막층에 형성하되 부유물 내부에 해당하는 영역 내에 복수개의 통전홀을 형성하는 단계와, 산화막층에 형성시키되 통전홀을 통하여 기판과 연통되는 실리콘층을 형성하는 단계와, 실리콘층에 부유물의 형상을 패터닝하는 단계와, 패터닝 된 부유물의 영역 내의 산화막층을 제거하는 단계와, 실리콘층 표면에 열산화막을 형성하는 단계, 및 열산화막을 제거하여 부유물을 형성하는 단계를 포함한다.

公开(公告)号：KR1020050033071A

公开(公告)日：2005-04-08

申请号：KR1020057002124

申请日：2003-08-14

Applicant: 페르킨엘머 테크놀로지스 게엠베하 운트 코. 가게

Inventor： 하우스너,마르틴

IPC: H01L21/32

CPC classification number: H01L21/3065 ,  B81C1/00626 ,  B81C2201/0132 ,  B81C2201/0142 ,  H01L21/30655 ,  H01L21/3081

Abstract: The invention relates to a method for selectively removing material from the surface of a substrate in order to form a recess, comprising the following steps: applying a mask to the surface of the substrate in accordance with the desired selective removal, and; dry etching the substrate, whereby metal, preferably aluminum, is used as a masking material. Energy can be inductively injected into a plasma.

Abstract translation: 本发明涉及一种用于选择性地从衬底的表面除去材料以形成凹陷的方法，包括以下步骤：根据所需的选择性去除将掩模施加到衬底的表面;以及 干蚀刻基板，由此使用金属，优选铝作为掩模材料。 能量可以感应注入等离子体。

公开(公告)号：KR1020000050852A

公开(公告)日：2000-08-05

申请号：KR1019990000980

申请日：1999-01-15

Applicant: 삼성전기주식회사

Inventor： 백석순 ,  하병주 ,  오용수

IPC: H01L29/84

CPC classification number: B81B3/0086 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81C2201/0104 ,  B81C2201/0132

Abstract: PURPOSE: A method for manufacturing a micro inertial sensor is provided to improve reliability and capability by processing a thick silicon joined to a glass in a high section ratio so that a measured surface and thickness becomes large, to eliminate parasitic capacitance generally caused by a silicon substrate by using glass as a substrate instead of silicon, and to reduce a manufacturing cost by a simple process using a mask. CONSTITUTION: A method for manufacturing a micro inertial sensor comprises the steps of: bonding a bulk silicon on a glass substrate; polishing the bonded bulk silicon to a desired thickness; forming an inertial sensor structure by etching the polished bulk silicon by an anisotropic etching method; forming a vacuum space by etching glass of a bottom portion of the silicon inertial sensor structure; and evaporating metal for an electrode on the entire surface of the etched chips.

Abstract translation: 目的：提供一种制造微惯性传感器的方法，以通过以高截面比加工连接到玻璃的厚硅，以便测量的表面和厚度变大，从而提高可靠性和能力，以消除通常由硅引起的寄生电容 通过使用玻璃作为基板代替硅，并且通过使用掩模的简单工艺来降低制造成本。 构成：微惯性传感器的制造方法包括以下步骤：将体硅结合在玻璃基板上; 将粘结体硅抛光至所需厚度; 通过各向异性蚀刻方法蚀刻抛光的体硅来形成惯性传感器结构; 通过蚀刻硅惯性传感器结构的底部的玻璃来形成真空空间; 并在蚀刻芯片的整个表面上蒸发用于电极的金属。

公开(公告)号：EP3409639A1

公开(公告)日：2018-12-05

申请号：EP18174480.6

申请日：2018-05-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： FUJII, Hidetoshi

IPC: B81C1/00

CPC classification number: B81C1/00619 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00587 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0142 ,  B81C2201/0198 ,  B81C2201/053

Abstract: The disclosure relates to a method for manufacturing recessed micromechanical structures in a MEMS device wafer. First vertical trenches in the device wafer define the horizontal dimensions of both level and recessed structures. The horizontal face of the device wafer and the vertical sidewalls of the first vertical trenches are then covered with a self-supporting etching mask which is made of a self-supporting mask material, which is sufficiently rigid to remain standing vertically in the location where it was deposited even as the sidewall upon which it was deposited is etched away. Recess trenches are then etched under the protection of the self-supporting mask. The method allows a spike-preventing aggressive etch to be used for forming the recess trenches, without harming the sidewalls in the first vertical trenches.

公开(公告)号：EP3210937B1

公开(公告)日：2018-09-05

申请号：EP17158214.1

申请日：2017-02-27

Applicant: SmartTip B.V.

Inventor： SARAJLIC, Edin

IPC: B81C1/00 ,  A61B5/15 ,  A61B5/151 ,  A61M37/00 ,  C01B21/068

CPC classification number: B81C1/0015 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150396 ,  A61B5/150511 ,  A61B5/150519 ,  A61B5/150984 ,  A61B5/15142 ,  A61M37/0015 ,  B81B2201/057 ,  B81B2201/12 ,  B81B2203/0118 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00111 ,  B81C1/00119 ,  B81C2201/0132 ,  B81C2201/0143 ,  B81C2201/0159 ,  B81C2201/0198 ,  C01B21/0687

Abstract: A method of manufacturing a plurality of through-holes (132) in a layer of first material, for example for the manufacturing of a probe (100) comprising a tip containing a channel. To manufacture the through-holes (132) in a batch process, - a layer of first material is deposited on a wafer (200) comprising a plurality of pits (210) - a second layer is provided on the layer of first material, and the second layer is provided with a plurality of holes at central locations of the pits (210); - using the second layer as a shadow mask when depositing a third layer (240) at an angle, covering a part of the first material with said third material (240) at the central locations, and - etching the exposed parts of the first layer using the third layer (240) as a protective layer.

公开(公告)号：EP2795671B1

公开(公告)日：2018-04-18

申请号：EP12821152.1

申请日：2012-12-21

Applicant: Micronit Microfluidics B.V.

Inventor： VAN 'T OEVER, Ronny ,  BLOM, Marko Theodoor ,  HANEVELD, Jeroen ,  OONK, Johannes ,  OLDE RIEKERINK, Marinus Bernardus ,  TIJSSEN, Peter ,  TIGELAAR, Hendrik Jan Hildebrand ,  FEHR, Jean-Noël ,  ROULET, Jean-Christophe ,  GUPTA, Amitava

IPC: H01L23/10 ,  B81C1/00 ,  H01L21/50 ,  C23F1/02 ,  B81C3/00

CPC classification number: B81C1/00269 ,  B81B2201/058 ,  B81C3/001 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/019 ,  C23F1/02 ,  H01L21/50 ,  H01L23/10 ,  H01L2924/0002 ,  Y10T428/239 ,  H01L2924/00

Abstract: The invention relates to method for bonding at least two substrates, for example made from glass, silicon or ceramic, by using an intermediate thin film metal layer for providing the bonding, said method comprising the following steps of: a) providing said two substrates; b) depositing said thin film metal layer on at least a part of a surface of a first substrate of the two substrates; c) bringing a surface of the second substrate into contact with said thin film metal layer on said surface of the first substrate such that a bonding between the second substrate and the thin film metal layer on the first substrate is provided; and d) at least locally strengthening the bonding between the second substrate and the thin film metal layer on the first substrate. The invention also relates to a device comprising two substrates, for example made from glass, silicon or ceramic, and an intermediate thin film metal layer.

公开(公告)号：EP3134916A1

公开(公告)日：2017-03-01

申请号：EP15782575.3

申请日：2015-04-22

Applicant: Master Dynamic Limited

Inventor： WANG, Yingnan ,  HUANG, Jianxing

IPC: H01L21/308 ,  B81C1/00

CPC classification number: B28D5/04 ,  B81C1/00626 ,  B81C2201/0132 ,  C09K13/08 ,  G03F7/405

Abstract: A method of forming a multi-level component having a first surface portion a first level and a second surface portion of a second level different to the level of the first level, said method including the steps of forming at least one arrangement of micro trenches or an arrangement of micro pillars having a micro trench therebetween in a predetermined arrangement in a mask material by one or more lithography processes, wherein one or more of said micro trenches have a first aspect ratio and one or more of said micro trenches have a second aspect ratio different from said first aspect ratio; applying one or more etching processes to a surface of a component upon which said mask is applied, wherein the component is etched by an aspect ratio dependent etch (ARDE) process so as to form an arrangement of micro trenches and micro pillars between adjacent micro trenches; wherein one or more micro trenches corresponding to the micro trenches of the first aspect ratio is etched a first level from said surface of the component, and wherein one or more micro trenches corresponding to the micro trenches of the second aspect ratio is etched at a second level from said surface of the component and at different level to said fist level; and (iii) removing said arrangement of micro pillars from said component by a removal process; wherein upon removal of said micro pillars a first surface portion is formed at said first level and a second surface portion is formed at said second level, wherein the second surface portion is at a different level to that of the of the first surface portion.

Abstract translation: 形成多级组件的方法包括：通过光刻工艺形成在掩模材料以预定排列微沟槽中的至少一个装置的步骤。 另一个步骤包括将一个或多个蚀刻工艺，以在其上掩模施加部件的表面。 所述微沟槽具有第一或第二不同的纵横比。 在所述施加步骤中，部件是通过在纵横比相关刻蚀（ARDE）工艺来蚀刻，从而形成微沟槽和相邻的微沟槽之间的微柱的布置。 另一个步骤包括通过去除工艺除去从组件微柱的布置。 因此，存在雅丁对上述方法与在第一级和与第一电平不同的电平进一步的另外的部分的第一部分的多级组件。