公开(公告)号：EP3195707A1

公开(公告)日：2017-07-26

申请号：EP14758210.0

申请日：2014-08-12

Applicant: Advanced Bionics AG

Inventor： LI, Lin ,  XIE, Jian ,  WALTER, Jeryle

IPC: H05K3/32 ,  H01R4/02

CPC classification number: H05K3/328 ,  A61N1/36036 ,  A61N1/3754 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/1028 ,  H05K2201/10287 ,  H05K2201/10303 ,  H05K2201/10424 ,  H05K2201/10795 ,  H05K2201/10909 ,  H05K2201/10916 ,  H05K2203/0169 ,  H05K2203/0195 ,  Y10T29/49183

Abstract: Methods of connecting wires (126) to feedthrough pins (104) and apparatus including wires connected to feedthrough pins.

Abstract translation: 将导线（126）连接到馈通引脚（104）和包括连接到馈通引脚的导线的装置的方法。

公开(公告)号：EP2899751A4

公开(公告)日：2016-06-22

申请号：EP13839334

申请日：2013-05-17

Applicant: NGK SPARK PLUG CO

Inventor： HAYASHI TAKAHIRO ,  NAGAI MAKOTO ,  MORI SEIJI ,  NISHIDA TOMOHIRO ,  WAKAZONO MAKOTO ,  ITO TATSUYA

IPC: H01L23/12 ,  G03F7/038 ,  G03F7/20 ,  H01L21/60 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46

CPC classification number: H05K1/111 ,  G03F7/038 ,  G03F7/20 ,  G03F7/2024 ,  G03F7/30 ,  H01L23/49822 ,  H01L2224/16237 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/09409 ,  H05K2201/09427 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2201/099 ,  H05K2201/10674 ,  H05K2203/058 ,  H05K2203/0594 ,  H05K2203/1476

Abstract: To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10. The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting terminal portions 41 for flip-chip mounting a semiconductor chip. The plurality of connecting terminal portions 41 is exposed through an opening portion 43 of a solder resist layer 25. Each connecting terminal portion 41 includes a connection region 51 for a semiconductor chip and a wiring region 52 disposed to extend from the connection region 51 along the planar direction. The solder resist layer 25 includes, within the opening portion 43, a side-surface covering portion 55 that covers the side surface of the connecting terminal portion 41 and a projecting wall portion 56 that is integrally formed with the side-surface covering portion 55 and disposed to project so as to intersect with the connection region 51.

公开(公告)号：EP2882267A3

公开(公告)日：2015-10-28

申请号：EP15153328.8

申请日：2013-01-24

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Muramatsu, Shigetsugu ,  Shimizu, Hiroshi ,  Kobayashi, Kazutaka

IPC: H05K3/00 ,  H05K3/20 ,  H01L33/60 ,  H05K1/02 ,  H01L25/075

CPC classification number: H01L33/60 ,  H01L25/0753 ,  H01L2224/13 ,  H01L2924/0002 ,  H05K1/0274 ,  H05K3/0014 ,  H05K3/0061 ,  H05K3/10 ,  H05K3/205 ,  H05K2201/0195 ,  H05K2201/0376 ,  H05K2201/09409 ,  H05K2201/10106 ,  H05K2201/2054 ,  Y10T29/49155 ,  H01L2924/00

Abstract: There is provided a wiring substrate (1). The wiring substrate includes: a heat sink (10); an insulating layer (20) on the heat sink; a reflective layer (30) on the insulating layer; a wiring pattern (40) embedded in the reflective layer and including a first surface (40A), a second surface opposite to the first surface and a side surface, the second surface and the side surface contacting the reflective layer; and a metal layer (50) on the first surface of the wiring pattern, wherein an exposed surface (50A) of the metal layer is flush with an exposed surface of the reflective layer.

Abstract translation: 提供了一种布线基板（1）。 布线基板包括：散热器（10）; 散热器上的绝缘层（20） 在绝缘层上的反射层（30） （40），所述布线图案嵌入所述反射层中并且包括第一表面（40A），与所述第一表面和侧表面相对的第二表面，所述第二表面和所述侧表面接触所述反射层; 和位于布线图案的第一表面上的金属层（50），其中金属层的暴露表面（50A）与反射层的暴露表面齐平。

公开(公告)号：EP2529605A4

公开(公告)日：2013-08-07

申请号：EP11736612

申请日：2011-01-17

Applicant: BYD CO LTD ,  SHENZHEN BYD AUTO R & D CO LTD

Inventor： XIE BINGBIN ,  PANG DAOCHENG

IPC: H05K1/11

CPC classification number: H05K1/117 ,  H01R13/03 ,  H01R13/04 ,  H01R13/113 ,  H05K2201/09381 ,  H05K2201/09409 ,  H05K2201/09709

Abstract: A contact piece of a gold finger comprises: a first main body segment; a second main body segment; and a transition segment connected to the first main body segment and the second main body segment, respectively, in a vertical direction, in which an upper edge and a lower edge of the transition segment are inclined with respect to a lateral direction respectively. A gold finger and a connector comprising the same are also provided.

Abstract translation: 金手指的接触片包括：第一主体部分; 第二主体段; 以及过渡段分别在垂直方向上连接到第一主体段和第二主体段，其中过渡段的上边缘和下边缘分别相对于横向方向倾斜。 还提供了金手指和包括该金手指的连接器。

公开(公告)号：EP2218144A2

公开(公告)日：2010-08-18

申请号：EP08846823.6

申请日：2008-10-30

Applicant: FCI

Inventor： JOHNESCU, Douglas M. ,  MINICH, Steven ,  SMITH, Stephen B.

IPC: H01R12/16

CPC classification number: H01R13/6471 ,  H01R12/51 ,  H01R12/7082 ,  H01R12/71 ,  H01R13/514 ,  H01R13/6477 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/325 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10189 ,  H05K2201/1059 ,  Y10T29/49222

Abstract: Disclosed are electrical connectors and methods of assembling an electrical connector having 'standard' (i.e., with electrical contacts having in-line tails), jogged (i.e., with electrical contacts having jogged tails but not connected orthogonally to another connector through a substrate), and/or 'orthogonal' (i.e., with electrical contacts having jogged tails that are used in an orthogonal application) leadframe assemblies in the same connector. This provides the flexibility of using some of the available contacts in an orthogonal application and, at the same time, having remaining contacts available for routing on the midplane PCB. Though this could be done using only orthogonal leadframe assemblies, the combination of standard leadframe assemblies with orthogonal leadframe assemblies creates additional spacing between the PCB vias, so that signal traces can be more easily routed on the midplane PCB.

公开(公告)号：EP1219437B2

公开(公告)日：2009-04-01

申请号：EP01130240.3

申请日：2001-12-19

Applicant: Seiko Epson Corporation

Inventor： Ishizawa, Taku ,  Fukano, Takakazu ,  Saruta, Toshihisa

IPC: B41J2/175

CPC classification number: B41J2/17546 ,  B41J2/17503 ,  B41J2/17526 ,  B41J2/1753 ,  H05K1/117 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10159

公开(公告)号：EP1953822A1

公开(公告)日：2008-08-06

申请号：EP08250357.4

申请日：2008-01-30

Applicant: Nitto Denko Corporation

Inventor： Tani, Emiko c/o Nitto Denko Corporation ,  Ishimaru, Yasuto c/o Nitto Denko Corporation ,  Mizutani, Toru c/o Nitto Denko Corporation

IPC: H01L23/498 ,  H05K1/02

CPC classification number: H01L23/49572 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/118 ,  H05K2201/09409 ,  H05K2201/09727 ,  H05K2201/10681 ,  H05K2203/1545 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A plurality of wiring patterns (12a-12f) are formed so as to extend in parallel with each other. A plurality of test terminals are formed in a substantially rectangular shape such that respective widths thereof increase toward respective one sides from respective ends of the plurality of wiring patterns. The plurality of test terminals in each group are arranged so as to be aligned along a length direction of the wiring patterns. The wiring patterns are formed so as to be longer in the order, and the test terminals are further away from a mounting region in the order. An interval (width of a plating resist) between the test terminals in each group and the wiring patterns in the other group adjacent thereto is set to decrease in the order. The invention also relates to a manufacturing method for said wiring patterns and test terminals.

Abstract translation: 多个布线图案（12a-12f）形成为彼此平行地延伸。 多个测试端子形成为大致矩形形状，使得其各自的宽度从多个布线图案的各个端部朝向相应的一侧增大。 每组中的多个测试端子被布置成沿着布线图案的长度方向排列。 这些布线图案按顺序形成为更长，并且测试端子依次进一步远离安装区域。 每组中的测试端子之间的间隔（电镀抗蚀剂的宽度）和与其相邻的另一组中的布线图案按顺序设定为减小。 本发明还涉及一种用于所述布线图案和测试端子的制造方法。

公开(公告)号：EP1635317A1

公开(公告)日：2006-03-15

申请号：EP05255404.5

申请日：2005-09-02

Applicant: LG Electronic Inc.

Inventor： Lee, Yong Han

IPC: G09G3/28 ,  H01J17/49 ,  H01L23/48 ,  H05K1/11

CPC classification number: H01J11/46 ,  G09G3/288 ,  G09G5/006 ,  G09G2300/0426 ,  G09G2320/0223 ,  H01J11/12 ,  H01L2924/0002 ,  H05K1/117 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09409 ,  H05K2201/09709 ,  H01L2924/00

Abstract: A plasma display apparatus includes a panel (1) having two or three rows of contact pads (213,213') for contacting the electrodes of the panel. This allows to increase the width of the pads whilst maintaining the distances between the electrodes. Thereby, align tolerance can be secured.

Abstract translation: 等离子体显示装置包括具有用于接触面板的电极的两排或三排接触垫（213,213'）的面板（1）。 这允许在保持电极之间的距离的同时增加焊盘的宽度。 因此，可以确保对准公差。

公开(公告)号：EP1219437A3

公开(公告)日：2002-11-06

申请号：EP01130240.3

申请日：2001-12-19

Applicant: SEIKO EPSON CORPORATION

Inventor： Ishizawa, Taku ,  Fukano, Takakazu ,  Saruta, Toshihisa

IPC: B41J2/175

CPC classification number: B41J2/17546 ,  B41J2/17503 ,  B41J2/17526 ,  B41J2/1753 ,  H05K1/117 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10159

Abstract: Circuit board (10) is of substantially rectangular shape, provided in the upper half of the juxtaposed face (13) with a substantially circular test terminal (20). In the lower half are provided a plurality of substantially rectangular terminals (21-27), arrayed in two rows, i.e., an upper and lower row, the upper row containing an I/O terminal (21) for data input/output, a power supply terminal (22) for supplying power, and a chip select terminal (23) for input of a chip select signal CS. The lower row of juxtaposed face (13) contains a ground terminal (24), a read/write terminal (25) for inputting read/write control signals W/R, a clock terminal (26) for inputting a clock signal CLK, and a ground terminal (27).

Abstract translation: 电路板（10）基本为矩形，在并列面（13）的上半部分设有一个基本为圆形的测试端子（20）。 在下半部分设置有排成两排（即上排和下排）的多个基本上矩形的端子（21-27），上排包含用于数据输入/输出的I / O端子（21）， 用于供电的电源端子（22）和用于输入芯片选择信号CS的芯片选择端子（23）。 下排并置面（13）包含接地端（24），用于输入读/写控制信号W / R的读/写端（25），用于输入时钟信号CLK的时钟端（26），以及 一个接地端子（27）。

公开(公告)号：EP1219437A2

公开(公告)日：2002-07-03

申请号：EP01130240.3

申请日：2001-12-19

Applicant: SEIKO EPSON CORPORATION

Inventor： Ishizawa, Taku ,  Fukano, Takakazu ,  Saruta, Toshihisa

IPC: B41J2/175

CPC classification number: B41J2/17546 ,  B41J2/17503 ,  B41J2/17526 ,  B41J2/1753 ,  H05K1/117 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10159

Abstract: Circuit board (10) is of substantially rectangular shape, provided in the upper half of the juxtaposed face (13) with a substantially circular test terminal (20). In the lower half are provided a plurality of substantially rectangular terminals (21-27), arrayed in two rows, i.e., an upper and lower row, the upper row containing an I/O terminal (21) for data input/output, a power supply terminal (22) for supplying power, and a chip select terminal (23) for input of a chip select signal CS. The lower row of juxtaposed face (13) contains a ground terminal (24), a read/write terminal (25) for inputting read/write control signals W/R, a clock terminal (26) for inputting a clock signal CLK, and a ground terminal (27).