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21.发明公开
公开(公告)号：EP4375842A1
公开(公告)日：2024-05-29
申请号：EP23853680.9
申请日：2023-04-04
Inventor： DAI, Jin , ZHANG, Yunsen
CPC classification number: Y02D10/00
Abstract: A storage system and a computational storage processor thereof, a solid-state drive and data reading and writing methods. The storage system includes a solid-state drive (SSD) and a computational storage processor (CSP), and communication between the SSD and the CSP, communication between the SSD and the external of the storage system, and communication between the CSP and the external of the storage system are performed through a point-to-point communication protocol of a peripheral component interconnect express (PCIe) bus; the CSP is configured to receive a first operation instruction based on a storage object from the external, generate a second operation instruction based on a flash memory address according to information carried by the first operation instruction and SSD resource information maintained locally, and send the second operation instruction to the SSD; and the SSD is configured to, after receiving the second operation instruction, exchange the data of the storage object with the external according to information carried by the second operation instruction.
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公开(公告)号：EP4213210A1
公开(公告)日：2023-07-19
申请号：EP22741413.3
申请日：2022-02-24
Inventor： XIAO, Deyuan , SHAO, Guangsu
IPC: H01L27/108 , H01L21/8242
Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: an array region, where the array region is provided with a plurality of active pillars; a plurality of bit lines extending along a first direction, where the bit line is located at a bottom of the active pillar; and a plurality of word lines extending along a second direction, where any one of the word lines covers sidewalls of a column of the active pillars arranged along the second direction; and the first direction and the second direction form a predetermined angle, and the predetermined angle is an acute angle or an obtuse angle.
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公开(公告)号：EP4167273A1
公开(公告)日：2023-04-19
申请号：EP22737361.0
申请日：2022-02-24
Inventor： SHAO, Guangsu , XIAO, Deyuan , HAN, Qinghua , QIU, Yunsong , BAI, Weiping
IPC: H01L21/336 , H01L29/78
Abstract: The embodiments of the application provide a semiconductor structure and a method for forming a semiconductor structure. The method for forming the semiconductor structure includes the following operations. A base is provided, in which the base includes a substrate, a first semiconductor layer and a second semiconductor layer sequentially formed on one another. A plurality of first isolation structures spaced apart from each other and a plurality of second isolation structures spaced apart from each other are formed in the base, in which a source layer formed in the second semiconductor layer and a drain layer formed in the substrate are provided between any two adjacent first isolation structures of the plurality of first isolation structures, each of the plurality of first isolation structures extends in a first direction, and each of the plurality of second isolation structures extends in a second direction. A channel layer is formed in the first semiconductor layer, in which a through hole extending in a same direction as the first direction is provided between the channel layer and each of two first isolation structures adjacent to the channel layer. A gate structure is formed in the through hole.
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24.发明公开
公开(公告)号：EP4395490A1
公开(公告)日：2024-07-03
申请号：EP22934524.4
申请日：2022-06-02
Inventor： ZHU, Zhengyong , KANG, Bokmoon , WANG, Guilei , ZHAO, Chao
IPC: H10B12/00
Abstract: A semiconductor memory device (10) and a manufacturing method and a read/write method therefor, and an electronic device and a memory circuit. A transistor (11) is arranged in each memory unit (101) in the semiconductor memory device (10), wherein a gate electrode (115) and a secondary electrode (116) are arranged in the transistor (11), and the secondary electrode (116) is electrically connected to a drain electrode (112). When a write operation is performed, a first voltage is applied to the gate electrode (115) by means of a word line (31), and an electrical signal is then applied to a source electrode (113) by means of a bit line (32) and according to external input data; and when a read operation is performed, by using the effect of a voltage of the secondary electrode (116) on a threshold voltage of the transistor (11), a second voltage is applied to the secondary electrode (116) by means of the word line (31), and the magnitude of the second voltage is between a threshold voltage of when the transistor (11) stores "1" and a threshold voltage of when the transistor (11) stores "0", and data is then read by means of detecting the magnitude of an output current of a field effect transistor.
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25.发明公开
公开(公告)号：EP4375823A1
公开(公告)日：2024-05-29
申请号：EP22952885.6
申请日：2022-12-19
Inventor： DAI, Jin , ZHANG, Yunsen
IPC: G06F3/06
CPC classification number: Y02D10/00
Abstract: An object computing and storage system, a data processing method, and a client and a storage medium, which belong to the field of electrical digital data processing. The object computing and storage system comprises a storage control device, and a storage chip or a storage disk which is connected thereto, wherein the storage control device is a computing and storage management system and executes the following processing: receiving an external data processing request, and parsing information of a specified storage object, information of a specified function and information of input data, which pieces of information are carried in the data processing request; when it is determined that calling of the specified function for the specified storage object is supported, calling the specified function according to the input data to perform computation on data of the specified storage object; and returning a computation result to a sender of the data processing request.
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Patent Agency Ranking26.发明公开
公开(公告)号：EP4270489A1
公开(公告)日：2023-11-01
申请号：EP22751631.7
申请日：2022-03-31
Inventor： XIAO, Deyuan , YU, Yong , SHAO, Guangsu
IPC: H01L29/78
Abstract: Provided are a semiconductor structure and a method for manufacturing the same, a memory device and a method for manufacturing the same. The semiconductor structure includes at least one transistor. Each of the at least one transistor includes a channel including a first semiconductor layer and a second semiconductor layer disposed around the first semiconductor layer. The second semiconductor layer introduces strain into the channel.
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公开(公告)号：US20250110668A1
公开(公告)日：2025-04-03
申请号：US18754323
申请日：2024-06-26
Inventor： Kai ZHANG , Jin DAI , Yunsen ZHANG
IPC: G06F3/06
Abstract: A CXL memory module, a controller, a method for accessing data, and a storage system are provided, which relate to data storage technologies. The CXL memory module includes a controller and a group of memory chips connected to the controller. The controller has a KV interface based on a CXL protocol. The controller is configured to receive a KV instruction sent by an external device through the KV interface, store object-based data into a memory chip or acquire object-based data from a memory chip.
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公开(公告)号：US20250071968A1
公开(公告)日：2025-02-27
申请号：US18754367
申请日：2024-06-26
Inventor： Xuezheng AI , Xiangsheng WANG , Guilei WANG , Chao ZHAO , Wenhua GUI
IPC: H01L23/528 , H01L23/522 , H10B12/00
Abstract: A semiconductor device, manufacturing method therefor, and electronic equipment are provided. The manufacturing method includes: alternately depositing sacrificial layers and insulation layers to obtain a stacked structure; forming in the stacked structure a plurality of via holes distributed at intervals, and forming dummy word lines in the via holes; forming a first trench penetrating through the stacked structure every two via holes apart; forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line; forming conductive layers within the two grooves corresponding to each insulation layer, wherein a conductive layer within each groove surrounds two exposed dummy word lines; and disconnecting a conductive layer surrounding a dummy word line to form a first electrode and a second electrode of a transistor.
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公开(公告)号：US12120863B2
公开(公告)日：2024-10-15
申请号：US17845113
申请日：2022-06-21
CPC classification number: H10B12/033 , H01L28/75 , H01L28/90 , H10B12/31
Abstract: A semiconductor structure includes a substrate, a storage capacitor unit, a transistor, and an electrical connection structure. The storage capacitor unit is located at an array area and includes: N insulation posts, distributed in a direction parallel to a surface of the substrate; a bottom electrode layer; a top electrode layer, directly facing the bottom electrode layer; and a capacitor dielectric layer, located between the top and bottom electrode layers. One of the bottom or top electrode layers corresponding to the N insulation posts is a continuous film layer, and the other is discrete film layers. The transistor is located at a circuit area and includes a capacitor control terminal located in the substrate of the circuit area. The electrical connection structure is electrically connected to the capacitor control terminal, and extends from the circuit area to the array area to come into contact with a corresponding discrete film layer.
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公开(公告)号：US20240290678A1
公开(公告)日：2024-08-29
申请号：US18705226
申请日：2023-06-07
Inventor： Ming ZENG
CPC classification number: H01L23/3178 , H01L21/56
Abstract: Provided is a semiconductor structure. The semiconductor structure includes a substrate including a die region and a non-die region, wherein an accommodation recess is formed in a side of the substrate and positioned in the non-die region; a buffer disposed in the accommodation recess; a functional film layer disposed on the side, where the accommodation recess is formed, of the substrate; and a passivation layer covering the functional film layer and the substrate. A buffer cavity with an opening facing away from the substrate is formed in the buffer. An orthographic projection of the functional film layer on the substrate is within the die region. A first through-via is formed in the passivation layer. An orthographic projection of the first through-via on the substrate is at least partially overlapped with an orthographic projection of the opening on the substrate. The opening is in communication with the first through-via.
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