公开(公告)号：JP2001210656A

公开(公告)日：2001-08-03

申请号：JP2000390445

申请日：2000-12-22

Applicant: ST MICROELECTRONICS SA

Inventor： MATHIEU ROY

IPC: H01L21/332 ,  H01L21/225 ,  H01L21/331 ,  H01L21/76 ,  H01L21/761 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a vertical power element on a substrate formed of a lightly-doped silicon wafer. SOLUTION: Vertical holes are made on the surface of a lower side of the substrate. A second conductive type dopant which is opposite to the substrate is diffused from the holes. Similar holes are made on the surface of the upper side of the substrate, an isolating wall is regulated and second conductive type dopant which is heavily doped from the hole is diffused. The holes corresponding to the isolating wall are sufficiently close to a diffusion area, and they are connected in the lateral direction and the vertical direction.

公开(公告)号：JP2001189091A

公开(公告)日：2001-07-10

申请号：JP2000323380

申请日：2000-10-23

Applicant: ST MICROELECTRONICS SA

Inventor： CHEHADI MOHAMAD

IPC: G11C16/06 ,  G06K19/07 ,  G11C5/14 ,  H02M3/07

Abstract: PROBLEM TO BE SOLVED: To generate high voltage with less energy in a power source receiving electric power by radio. SOLUTION: An integrated circuit card is provided with voltage regulators 210, 230 receiving electric power with a form of a radio frequency signal SR and generating first power source voltage Vcc, and with a voltage booster circuit 232 receiving first power source voltage Vcc by a first power source input terminal 231, receiving second power source voltage being higher than the first power source voltage Vcc by a second power source input terminal 232, and generating high voltage HV.

公开(公告)号：JP2001086030A

公开(公告)日：2001-03-30

申请号：JP2000218501

申请日：2000-07-19

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  ENGUENT JEAN-PIERRE

IPC: G06K7/08 ,  G06K17/00 ,  G06K19/07 ,  H04B1/59 ,  H04B5/00

Abstract: PROBLEM TO BE SOLVED: To use a transponder and/or a terminal exclusively in a comparatively remote area by setting the characteristics of component elements of an oscillation circuit of the transponder to quickly attenuate the coupling coefficient between the oscillation circuits of both terminal and transponder when the distance set between the transponder and the terminal is smaller than a prescribed value. SOLUTION: When the distance between a transponder 10 and a terminal 1 is decreased, the coupling coefficient between the oscillation circuit of the transponder 10 and the terminal 1 is reduced quickly. The best measure of this problem shows that the optimum coupling point must be approximately equal to the center of a desirable distance operation area. When the distance between the transponder 10 and the terminal 1 deviates from the distance to the operation area, the coupling coefficient is quickly reduced and no power is supplied to the transponder 10 thereafter. The largest operation point is selected so that the voltage between the input terminals 11 and 12 of the transponder 10 lies in the interval between the voltage for which the least operating voltage of the transponder 10 corresponds to an inflection point and the voltage of the parallel oscillation circuit when the optimum coupling is secured between both oscillation circuits.

公开(公告)号：JP2000330788A

公开(公告)日：2000-11-30

申请号：JP2000135141

申请日：2000-05-08

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  BOUVIER STEPHANE

IPC: G06F9/32 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To decrease disadvantages in case of a failure in branching by previously holding a usable instruction to be executed by detecting a branch instruction and setting a branch shadow mode, and supplying the instruction continuously. SOLUTION: A program counter 80 is equipped with a takeout branch address unit 218 which holds a target address for branching. A general unit 21 transfers the target address to the takeout branch address unit 218 of a control unit 12 through a bus 23. Branch with a dummy guard is detected by a decoder 82 and the branch shadow mode is set. The branch shadow mode indicates that the setting is reset with a signal on a line 224 from the general unit 21 to the decoder and branching is determined. The branch shadow circuit constitution of the decoder 82 continues to supply instructions after the branch instruction with the dummy guard through a computer and the execution of all allowed following instructions is carried on.

公开(公告)号：JP2000299650A

公开(公告)日：2000-10-24

申请号：JP2000059264

申请日：2000-03-03

Applicant: ST MICROELECTRONICS SA ,  TELIA AB

Inventor： ISSON OLIVIER ,  NORDSTROEM TOMAS

IPC: H04L5/14 ,  H04B3/21 ,  H04B3/23 ,  H04J11/00 ,  H04L25/03 ,  H04L27/26 ,  H04M1/76 ,  H04M3/00

Abstract: PROBLEM TO BE SOLVED: To obtain a DSL transmission system of simple constitution by setting a period for processing a filter to an at least previously set time length. SOLUTION: An output symbol system S is subtracted from the output of a delay line 80 by a subtracting circuit 82, and a difference signal is supplied to an FIR filter 84 for realizing a transfer function h* for local echo inference. A filter 84 operates only to sampling data corresponding to a delaying time δor the maximum delaying time of a line and infers echo component from the difference between two continuous symbols. However, being a linear filter, the component is equivalent to the difference between the respective echo components of the two symbols. The output of the filter 84 is supplied for an adding circuit 86, and an input symbol S' receiving the influence of a nonlinear echo is simultaneously received. The circuit 86 supplies a desired orthogonal echo signal to a Fast Fourier Transforming(FFT) circuit 18 as an input signal IN'. Then, the filter 84 operates only in a short period at the starting point of each transmission symbol.

公开(公告)号：JP2000250816A

公开(公告)日：2000-09-14

申请号：JP19942698

申请日：1998-06-10

Applicant: ST MICROELECTRONICS SA

Inventor： TAILLIET FRANCOIS

IPC: G06F12/14 ,  G06F21/24 ,  G07F7/10

Abstract: PROBLEM TO BE SOLVED: To prevent the malfunction of an integrated circuit by activating a change in the response of the integrated circuit while using the ordinary instruction of the integrated circuit to be used for an application program, and detecting a scenario of that activation. SOLUTION: Another transmitter M3' connected parallel to a transistor M3 of a first arm is provided and a current Iref is let flow by the current mirror effect of a transistor M1. Then, that transistor M3' is connected to a ground and activated by a selecting transistor M5, a scenario of that activation is detected by the sequence of instructions received by an integrated circuit and according to that detected scenario, one response of the integrated circuit is changed. Thus, the integrated circuit can be programmed so as not to generate the malfunction and can be operated against illegal access.

公开(公告)号：JP2000236354A

公开(公告)日：2000-08-29

申请号：JP35731699

申请日：1999-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL ,  COPPOLA MARCELLO

IPC: H04L13/08 ,  G06F12/02 ,  G06F12/08 ,  G06F12/0875 ,  H04L12/933 ,  H04Q11/04 ,  H04L12/56 ,  H04L12/28 ,  H04L12/46

Abstract: PROBLEM TO BE SOLVED: To optimize access to a queue of idle blocks by filling a cache memory, including a partial queue of exclusively used idle blocks, from a main queue by a burst when its filling level reaches the lowest limit and emptying it for the main queue by the burst when the filling level reaches the highest limit. SOLUTION: The cache memory 20 is preferably an LIFO type. To manage the cache memory 20 of this type, a controller CTRL includes a register including a pointer topc indicating the uppermost part of the cache memory 20. When the pointer topc reaches the highest limit max, part of the contents of the cache memory 20 is transferred to an idle block queue 18 by the burst. When the pointer topc reaches the lowest limit min to the contrary, part of the idle block queue 18 is transferred by the burst to the cache memory 20.

公开(公告)号：JP2000200909A

公开(公告)日：2000-07-18

申请号：JP36690699

申请日：1999-12-24

Applicant: ST MICROELECTRONICS SA

Inventor： JEAN JALADE ,  JEAN-LOUIS SANCHEZ ,  LAUR JEAN-PIERRE ,  BREIL MARIE ,  AUSTIN PATRICK ,  BERNIER ERIC ,  MATHIEU ROY

IPC: H01L29/74 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L29/739 ,  H01L29/78 ,  H01L21/06

Abstract: PROBLEM TO BE SOLVED: To obtain a part of a minimum surface to a fixed maximum current by checking a thyristor type part. SOLUTION: An auxiliary thyristor 13 is a vertical thyristor, and a cathode corresponds to an N-type region N5 formed in a well likewise. A part of a region P4 between regions N4 and N5 is covered with an insulation gate G2 and regions N4-P4-N5 corresponds to an N-channel enhancement MOS transistor M. An IGBT 14 is made a multicellor part. When the surface of a rear is covered with a P-type layer P1, a vertical IGBT is formed, and a cathode corresponds to metallization formed on regions P6, N6 and an anode corresponds to a surface at a rear side of a part. For a cell corresponding to a well P6, conduction takes place starting from an anode A towards metallization which covers the source N6, and the region N5 and then towards the region N4 and a cathode K. Next, conduction of a thyristor is checked.

公开(公告)号：JP2000156403A

公开(公告)日：2000-06-06

申请号：JP29659399

申请日：1999-10-19

Applicant: ST MICROELECTRONICS SA

Inventor： ANCEAU CHRISTINE ,  PIERRE FABIEN ,  BONNARD OLIVIER

IPC: H01L21/76 ,  H01L21/225 ,  H01L21/761 ,  H01L21/763

Abstract: PROBLEM TO BE SOLVED: To create an effective insulation wall relatively easily, rapidly, and effectively by punching recesses being isolated mutually on a substrate from upper and lower portions to the contour of an insulation wall and filling the recesses with a material containing a conductive dopant, and performing annealing so that the conductive regions being diffused from adjacent recesses can be joined together. SOLUTION: Recesses being isolated mutually are punched in a substrate 1 according to the contour of a desirable insulation wall, are filled with a material including a second-conductive dopant, and are subjected to annealing so that a second conductive region being diffused from the adjacent recesses can be joined together. Then, a series of first recesses 20-22 and a series of second recesses 30-33 are formed from upper and lower surfaces, respectively. The recesses have a nearly rectangular section, where its larger dimension is vertical to the arrangement line of the recess and the depth is smaller than or equal to the thickness of the half of the substrate 1. When diffusion is formed from the rectangular region, a diffusion distance d1 in the direction of the long side of the rectangle is smaller than a diffusion distance d2 of a short side and an insulation wall is closed within limited diffusion time.

公开(公告)号：JP2000133789A

公开(公告)日：2000-05-12

申请号：JP29380599

申请日：1999-10-15

Applicant: ST MICROELECTRONICS SA

Inventor： JAOUEN HERVE ,  FERRANT RICHARD

IPC: G11C11/401 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM with which a power source and a ground are protected from charging variation of a memory element. SOLUTION: Cells 1-n of a memory circuit construction include MOS transistors M1-Mn and capacitors C1-Cn. An electrode 311 is connected in common to all cells of the same line and is covered with an insulator 312. The insulator is covered with independent conductive elements 313-1 and 313-2 which are diffused on the same horizontal plane. The two adjacent elements 313-1 and 313-2 are respectively biased at a high potential or a low potential. The low potential is a reference potential of the circuit, in which the cells are formed. The high potential is a potential Vdd for writing in the memory cells.