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公开(公告)号：KR101486984B1
公开(公告)日：2015-01-30
申请号：KR1020080107236
申请日：2008-10-30
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/1052 , G11C13/0004 , G11C2213/52 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683
Abstract: 가변 저항 메모리 소자 및 그 형성방법이 제공된다. 상기 가변 저항 메모리 소자의 형성방법은 반도체 기판 상에 제 1 층간절연막을 형성하고, 제 1 층간절연막내에 제 1 방향으로 연장된 장방형의 상부면을 가지는 하부전극을 형성하고, 하부전극 상에 제 1 방향과 교차하는 제 2 방향으로 연장되는 장방형의 하부면을 가지며 하부전극과 접촉하는 가변저항패턴을 형성하는 것을 포함하되, 하부전극과 가변저항패턴이 접촉하는 면적은 하부전극의 상부면의 단축길이와 가변저항패턴의 하부면의 단축길이의 곱으로 표현된다.
가변저항패턴, 하부전극, 계면 저항-
公开(公告)号：KR1020110002208A
公开(公告)日：2011-01-07
申请号：KR1020090059686
申请日：2009-07-01
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115 , H01L21/205
CPC classification number: H01L21/0228 , C23C16/34 , C23C16/45531 , H01L21/02153 , H01L21/28562 , H01L21/3141 , H01L21/76843 , H01L45/06 , H01L45/126 , H01L45/16 , H01L21/67184
Abstract: PURPOSE: A forming method of a semiconductor device is provided to easily control the composite and impurity of components within a film by replacing the substitutes and replacement gas. CONSTITUTION: A substrate is prepared within a reaction chamber. The first precursor including the first substituent and the replacement gas are offered within the reaction chamber. A second precursor is offered within the reaction chamber. A first substituent of the first precursor(100) is replaced with the replacement gas in the space being distanced from the substrate.
Abstract translation: 目的：提供一种半导体器件的形成方法，通过替换替代物和置换气体来容易地控制膜内部件的复合和杂质。 构成：在反应室内制备底物。 在反应室内提供包含第一取代基和置换气体的第一前体。 在反应室内提供第二个前体。 第一前体（100）的第一取代基被替换为在离开衬底的空间中的置换气体。
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公开(公告)号：KR100888617B1
公开(公告)日：2009-03-17
申请号：KR1020070059001
申请日：2007-06-15
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/144 , C23C16/34 , C23C16/45536 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/143 , H01L45/1616 , H01L45/1683
Abstract: 상변화 메모리 장치 및 그 형성 방법이 제공된다. 상기 형성 방법은 기판에 상변화 물질용 전구체들 및 질소를 포함하는 반응성 라디칼을 제공하여 상변화 물질막을 형성하는 단계를 포함한다.
상변화 메모리, 전구체, 반응성 라디칼-
公开(公告)号：KR1020090020391A
公开(公告)日：2009-02-26
申请号：KR1020070085126
申请日：2007-08-23
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/141
Abstract: A multi-level nonvolatile memory device, a program method thereof, and a fabricating method thereof are provided to heighten the reliability of the program operation by forming a plurality of bottom electrodes on the top of the substrate. A plurality of bottom electrodes(110) are formed on a substrate(100). The first insulating layer pattern(120) comprises a plurality of first openings(122) which are formed on the top of the substrate, and open a plurality of bottom electrodes. A plurality of bottom electrode contacts(130) are formed inside the first openings and on the bottom electrodes. A plurality of phase change material patterns(140) are formed inside the plurality of first openings and on the plurality of bottom electrode contacts. A plurality of upper electrode contacts(150) are formed on a plurality of phase change material patterns. The second insulating layer pattern(160) is formed on the first insulating layer pattern and the plurality of upper electrode contacts.
Abstract translation: 提供了一种多级非易失性存储器件及其编程方法及其制造方法，通过在衬底的顶部形成多个底部电极来提高编程操作的可靠性。 在基板（100）上形成多个底部电极（110）。 第一绝缘层图案（120）包括形成在基板的顶部上的多个第一开口（122），并且打开多个底部电极。 多个底部电极触点（130）形成在第一开口内部和底部电极上。 多个相变材料图案（140）形成在多个第一开口内部和多个底部电极触点上。 多个上电极触点（150）形成在多个相变材料图案上。 第二绝缘层图案（160）形成在第一绝缘层图案和多个上电极接触件上。
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公开(公告)号：KR1020080110348A
公开(公告)日：2008-12-18
申请号：KR1020070059001
申请日：2007-06-15
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/144 , C23C16/34 , C23C16/45536 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/143 , H01L45/1616 , H01L45/1683 , G11C13/0004
Abstract: A phase change memory device and a method of formation thereof are provided to form a phase change material layer at low temperature so that the high integration of a phase change memory device is possible. A formation method of the phase change memory device comprises: a step forming the first insulating layer(20) having the first opening(30) on the substrate(10); a step for forming a phase change material layer within a first opening by providing reactive radical including the precursors and nitrogen for the phase change material in substrate; a step for forming the second conductor on the phase change material layer; and a reactive radical has the chemical formula NRnH3-n or N2RnH4-n(0
Abstract translation: 提供相变存储器件及其形成方法以在低温下形成相变材料层，从而可以实现相变存储器件的高集成度。 相变存储器件的形成方法包括：在衬底（10）上形成具有第一开口（30）的第一绝缘层（20）的步骤; 在第一开口内形成相变材料层的步骤，通过提供反应性基团，所述反应性基团包括前体和氮气用于基材中的相变材料; 在相变材料层上形成第二导体的步骤; 反应性基团具有化学式NRnH3-n或N2RnH4-n（0≤n≤2，n为正数），R为烃基。
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Patent Agency Ranking
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公开(公告)号：KR101559912B1
公开(公告)日：2015-10-13
申请号：KR1020090027622
申请日：2009-03-31
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L45/1616 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
Abstract: 상변화메모리소자의형성방법을제공할수 있다. 이를위해서, 하부전극및 층간절연막을가지는반도체기판이준비될수 있다. 상기하부전극은층간절연막으로둘러싸일수 있다. 상기반도체기판을반도체증착장비의공정챔버내 안착시킬수 있다. 상기공정챔버내 소오스가스들, 반응가스및 퍼지가스를주입해서반도체기판상에상변화물질막을형성할수 있다. 상기소오스가스들은공정챔버에동시에주입될수 있다. 상기상변화물질막은층간절연막을통해서하부전극과접촉할수 있다. 상기층간절연막을노출시키도록상변화물질막을식각해서층간절연막에상변화메모리셀을형성할수 있다. 상기상변화메모리셀 상에상부전극을형성할수 있다.
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公开(公告)号：KR1020100109163A
公开(公告)日：2010-10-08
申请号：KR1020090027622
申请日：2009-03-31
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L45/1616 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683 , H01L45/143
Abstract: PURPOSE: A method of forming a phase change memory device is provided to supply electrical bit to a phase change device by forming a void in the phase change memory cell. CONSTITUTION: A first to third source gas(G1-G3) are inserted into a process chamber. The first source gas has a germanium precursor. A second source gas has an antimony precursor. A third source gas has a tellurium precursor. A reaction gas is inserted into a process chamber during the time of inserting the first to the third gas. A purge gas is inserted into the process chamber during the time of inserting the first to the third gas. A phase change material layer is filled into the opening the inter-layer insulating film of the semiconductor substrate.
Abstract translation: 目的：提供形成相变存储器件的方法，通过在相变存储器单元中形成空隙来向相变器件提供电位。 构成：将第一至第三源气体（G1-G3）插入处理室。 第一源气体具有锗前体。 第二源气体具有锑前体。 第三源气体具有碲前体。 在插入第一至第三气体期间，将反应气体插入处理室。 在插入第一至第三气体期间，将吹扫气体插入处理室。 将相变材料层填充到半导体衬底的层间绝缘膜的开口中。
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公开(公告)号：KR1020100066819A
公开(公告)日：2010-06-18
申请号：KR1020080125301
申请日：2008-12-10
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76816 , H01L27/24
Abstract: PURPOSE: A method for forming a contact structure, a method for manufacturing a semiconductor device using the same, and the semiconductor device are provided to minimize a reset current of a phase change memory device by minimizing an interfacial area between a phase change material film and an electrode. CONSTITUTION: A first molding pattern(24) including a first opening is formed on a substrate(1). An insulating film which covers the sidewall of the first opening is formed. A second molding pattern(30) which fills the rest of the first opening is formed. A mask exposing a part of the insulating layer is formed on the substrate including the second molding pattern. An insulating pattern(27a) is formed between the first and the second molding patterns. The exposed insulating layer is selectively etched.
Abstract translation: 目的：提供一种用于形成接触结构的方法，使用该接触结构的半导体器件的制造方法以及半导体器件，以通过使相变材料膜和相变材料膜之间的界面面积最小化来最小化相变存储器件的复位电流 电极。 构成：在基板（1）上形成包括第一开口的第一成型图案（24）。 形成覆盖第一开口的侧壁的绝缘膜。 形成填充第一开口的其余部分的第二模制图案（30）。 在包括第二成型图案的基板上形成露出绝缘层的一部分的掩模。 绝缘图案（27a）形成在第一和第二模制图案之间。 暴露的绝缘层被选择性地蚀刻。
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公开(公告)号：KR1020100048198A
公开(公告)日：2010-05-11
申请号：KR1020080107236
申请日：2008-10-30
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/1052 , G11C13/0004 , G11C2213/52 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683 , H01L45/143
Abstract: PURPOSE: A resistance variable memory device and a method for forming the same are provided to selectively reduce the interfacial resistance between a variable resistance pattern and a lower electrode by minimizing the area to which the lower electrode and the variable resistance pattern are contacted. CONSTITUTION: A first interlayer insulation layer(120) is formed on a semiconductor substrate. A lower electrode is formed in the first interlayer insulation layer. The rectangular upper side of the lower electrode is expanded to a first direction. A variable resistance pattern(160) is formed on the lower electrode. A first insulation layer(142) which covers the lower electrode is formed on the first interlayer insulation layer. The first insulation layer is patterned to form a first trench which is expanded to a second direction. A spacer which is expanded to the second direction is formed on the sidewall of the first trench. A second insulation layer(144) is formed in order to fill the first trench.
Abstract translation: 目的：提供电阻可变存储器件及其形成方法，以通过使下电极和可变电阻图案接触的面积最小化来选择性地降低可变电阻图案和下电极之间的界面电阻。 构成：在半导体衬底上形成第一层间绝缘层（120）。 在第一层间绝缘层中形成下电极。 下电极的矩形上侧被扩展为第一方向。 在下电极上形成可变电阻图案（160）。 覆盖下电极的第一绝缘层（142）形成在第一层间绝缘层上。 图案化第一绝缘层以形成扩展到第二方向的第一沟槽。 在第一沟槽的侧壁上形成有扩展到第二方向的间隔物。 形成第二绝缘层（144）以填充第一沟槽。
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