Abstract:
A COF substrate includes a base film, first upper conductive patterns, at least one second upper conductive pattern, and lower conductive patterns. The first upper conductive patterns are arranged in the upper surface of the base film. Each first upper conductive pattern includes a separated inner pattern and an outer pattern. The second conductive pattern is arranged to be located between the first upper conductive patterns in the upper surface of the base film. The lower conductive patterns are arranged in the lower surface of the base film and connect the inner pattern and the outer pattern. Therefore, the generation of the short between panel patterns having micro pitches is prevented by a COF substrate structure.
Abstract:
PURPOSE: Tape film package and manufacturing method thereof are provided to increase the production yield by preventing or minimizing generation of metal particles. CONSTITUTION: A via contact (40) penetrates an insulation film (10). First wire patterns (30) are extended from the via contact to a cross section of the insulation film. Second wire patterns (50) are connected to the via contact below the insulation film, are parallel with the first wire patterns and are spaced apart from the cross section of the insulation film. A second solder resist (52) covers a part of the second wire patterns. The second solder resist is arranged below the insulation film between the second wire patterns and cross section.
Abstract:
UHF 대역을 사용하는 RFID 리더 및 RFID 태그 그리고 그들의 동작방법이 개시된다. 본 발명에 따른 UHF 대역을 사용하는 RFID 리더는 RFID 태그에 송신할 데이터를 생성하는 데이터 생성부, RFID 태그를 제어할 명령어가 인증이 요구되는 명령어일 경우 데이터 생성부에 의해 소정의 인증코드를 포함하는 데이터를 생성하도록 제어하는 리더 제어부, 및 생성된 데이터를 RFID 태그에 송신하는 리더 송신부를 포함한다. 이에 의해, 특정 명령어에 대하여 RFID 리더 및 RFID 태그간의 통신상의 보안을 강화할 수 있다. RFID, 비접촉식, 태그, 리더, HMAC, 인증
Abstract:
본 발명은 칩 온 필름 패키지 및 이를 포함하는 장치 어셈블리에 관한 것이다. 본 발명에 따른 장치 어셈블리는 다수의 필름 관통 배선이 형성된 필름 기판을 포함하는 칩 온 필름 패키지; 다수의 패널 관통 배선이 형성된 패널 기판을 포함하며, 상기 칩 온 필름 패키지의 상부에 배치되어 일 단이 상기 칩 온 필름 패키지의 일 단과 전기적으로 연결된 패널부; 및 상기 패널부의 하부에 배치되어 일 단이 상기 칩 온 필름 패키지의 타 단과 전기적으로 연결된 제어부를 포함한다.
Abstract:
PURPOSE: A semiconductor package is provided to prevent a crack of a structure on the upper side of a heat sink by preventing stress from being concentrated near the end of the heat sink. CONSTITUTION: A semiconductor chip(70) is arranged on the upper side of a substrate. A heat sink(20) is arranged on the lower side of the substrate. A heat sink covering layer(30) is arranged on the lower side of the substrate and surrounds the heat sink. The heat sink covering layer includes materials with a lower young's modulus than the young's modulus of the heat sink.
Abstract:
PURPOSE: A heating member tape, a COF type semiconductor package equipping the heating member and an electronic device applying the same are provided to secure a heating path by fixing the heating member without separating the heating member and the contact member. CONSTITUTION: A COF(Chip On Film) semiconductor package includes an insulating substrate(13), a semiconductor device(11), an heat member(17), and a space. The insulating substrate has a flexibility characteristic. The semiconductor device is arranged to the upper side of the insulating substrate. The heat member is arranged to the lower surface on the insulating substrate. The space is formed between the lower surface and heat member of the insulating substrate.
Abstract:
The semiconductor chip and lead are electrically connected by using bump by replacing a wiring formed in the semiconductor chip with a lead formed in a region which is not used in the film substrate. Accordingly, the wiring in semiconductor chip can be removed and the size of the semiconductor chip can be reduced. In the semiconductor package(100) having the semiconductor chip(150) on the substrate(110), is formed, the substrate includes the first and the second bonding region bonded with the semiconductor chip and the pattern replacing the wiring of the semiconductor chip between the first and the second bonding region. The first lead is electrically connected with the semiconductor chip in the first bonding region(120). The second lead is electrically connected with the semiconductor chip in the second bonding region(122).