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公开(公告)号：KR100429515B1
公开(公告)日：2004-05-03
申请号：KR1020010085810
申请日：2001-12-27
Applicant: 삼성전자주식회사
IPC: H01L31/12
Abstract: PURPOSE: A method for fabricating optical communication elements including a mushroom-shaped plating layer is provided to form a bonding pad on a plating layer without an additional photoresist layer by forming a thick mushroom-shaped plating layer to an upper portion of the photoresist layer. CONSTITUTION: The first metal layer(22) is formed on a semiconductor substrate(21). A photoresist layer is formed on the first metal layer. A through-hole is formed by etching a predetermined portion of the photoresist layer. A mushroom-shaped plating layer(24) is formed on the first metal layer exposed by the through-hole. The second metal layer(25b) is formed on the mushroom-shaped plating layer and the photoresist layer. The photoresist layer is removed therefrom. The second metal layer is removed from the semiconductor substrate.
Abstract translation: 目的：提供一种制造包括蘑菇形镀层的光通信元件的方法，以通过在光刻胶层的上部形成厚的蘑菇形镀层而在没有附加光刻胶层的情况下在镀层上形成键合焊盘。 构成：第一金属层（22）形成在半导体衬底（21）上。 在第一金属层上形成光致抗蚀剂层。 通过蚀刻预定部分的光致抗蚀剂层来形成通孔。 蘑菇形镀层（24）形成在由通孔暴露的第一金属层上。 第二金属层（25b）形成在蘑菇形镀层和光致抗蚀剂层上。 光致抗蚀剂层从中被去除。 第二金属层从半导体衬底移除。
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公开(公告)号：KR101862547B1
公开(公告)日：2018-05-31
申请号：KR1020120038398
申请日：2012-04-13
Applicant: 삼성전자주식회사
IPC: H01L21/205
CPC classification number: H01L29/66666 , C23C16/24 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02494 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02595 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/28556 , H01L21/76876 , H01L21/76877 , H01L27/10888 , H01L27/11582
Abstract: 폴리실리콘막형성방법에있어서, 공정챔버내에로딩된대상체상에질소함유실리콘전구체를도입하여예비씨드층을형성한다. 예비씨드층상에염소함유실리콘전구체를도입하여씨드층을형성한다. 씨드층상에실리콘소스를도입하여폴리실리콘막을형성한다.
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公开(公告)号：KR1020160025165A
公开(公告)日：2016-03-08
申请号：KR1020140111858
申请日：2014-08-26
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L21/336
CPC classification number: H01L21/321 , H01L27/11524 , H01L27/11556 , H01L27/11582 , H01L29/495 , H01L29/7827
Abstract: 본발명의실시예에따른반도체장치의제조방법은, 산화된표면층을갖는금속층을포함하는기판을열처리챔버내에장착하는단계, 열처리챔버내에수소라디칼을생성하는단계, 및수소라디칼을이용해금속층의산화된표면층을환원하는단계를포함할수 있다.
Abstract translation: 根据本发明的实施例的半导体器件的制造方法可以包括以下步骤：将包括具有氧化表面层的金属层的衬底安装在热处理室中; 在热处理室中产生氢根; 并使用氢自由基对金属层的氧化表面层进行脱氧。 本发明的目的是提供半导体器件的制造方法，其可以通过防止半导体器件的栅电极的氧化来抑制栅电极的电阻的增加。
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公开(公告)号：KR1020160000512A
公开(公告)日：2016-01-05
申请号：KR1020140077241
申请日：2014-06-24
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11573 , H01L27/11521 , H01L27/11526 , H01L27/11568 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/16 , H01L29/788 , H01L29/792
Abstract: 본발명의실시형태에따른메모리장치는, 제1 기판상에마련되는복수의회로소자를갖는주변회로영역, 및상기제1 기판의상부에배치되는제2 기판의상면에수직하는방향으로연장되는채널영역과, 상기채널영역에인접하도록상기제2 기판상에적층되는복수의게이트전극층및 복수의절연층을갖는셀 영역을포함하며, 상기제1 기판의적어도일부영역은상기제2 기판과접촉하며, 상기제1 기판과상기제2 기판은하나의기판을제공한다.
Abstract translation: 根据本发明的实施例，存储器件包括：具有在第一衬底上制备的多个电路元件的外围电路区域; 以及单元区域，包括在与配置在第一基板的上部的第二基板的上表面垂直的方向上延伸的沟道区域，以及堆叠在第二基板上的多个栅电极层和多个绝缘层， 与沟道区相邻，其中第一衬底的至少一部分与第二衬底接触，并且第一衬底和第二衬底提供一个衬底。
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Patent Agency Ranking
公开(公告)号：KR1020100081145A
公开(公告)日：2010-07-14
申请号：KR1020090000438
申请日：2009-01-05
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/7881 , H01L21/28273 , H01L29/42336 , H01L29/66825 , H01L21/28185 , H01L21/28202 , H01L21/31051
Abstract: PURPOSE: A non-volatile memory device and a method of forming the same are provided to prevent the diffusion of impurity ions into a semiconductor substrate from the p-type floating gate by forming diffusion stop poly pattern under the p-type floating gate. CONSTITUTION: An element isolation film(50) defining an active area(60) is formed in a semiconductor substrate(10). A concave part is formed between the element isolation film and the active area. A floating gate(115) is formed on the active area. A control gate(150) is formed on the floating gate. A diffusion-stop poly pattern(105) is formed in around the floating gate. The diffusion-stop poly pattern is conformally arranged along the concave part.
Abstract translation: 目的：提供一种非易失性存储器件及其形成方法，以通过在p型浮置栅极下形成扩散阻挡多晶硅图案来防止杂质离子从p型浮置栅极扩散到半导体衬底中。 构成：在半导体衬底（10）中形成限定有源区（60）的元件隔离膜（50）。 在元件隔离膜和有源区之间形成凹部。 浮动栅极（115）形成在有源区域上。 在浮动栅极上形成控制栅极（150）。 在浮动栅极周围形成扩散停止多晶型（105）。 扩散停止多晶型图案沿着凹部保形地布置。
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公开(公告)号：KR1020100055863A
公开(公告)日：2010-05-27
申请号：KR1020080114749
申请日：2008-11-18
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/11521 , H01L21/02057 , H01L21/28202 , H01L21/28273 , H01L21/31051 , H01L21/76224
Abstract: PURPOSE: A method for manufacturing a nonvolatile memory is provided to improve a threshold voltage distribution of a cell transistor by forming a thicker tunneling oxidation layer on the edge than the center on an active region. CONSTITUTION: An active region(105) is limited by forming a trench by etching a part of a substrate. The edge of the active region is exposed from a buffer layer. A device isolation layer(160) is formed to cover the exposed edge of the active region in the trench. The edge of the active region is exposed by removing a hard mask and a pad oxidation layer. A first insulation layer is formed on the exposed edge of the active region. A second insulation layer is formed on the expose upper side of the active region. The second insulation layer is thinner than the first insulation layer. A conductive pattern is formed on the first and second insulation layers.
Abstract translation: 目的：提供一种用于制造非易失性存储器的方法，以通过在边缘上形成比活性区域上的中心更厚的隧道氧化层来改善单元晶体管的阈值电压分布。 构成：通过蚀刻衬底的一部分来形成沟槽来限制有源区（105）。 有源区域的边缘从缓冲层露出。 形成器件隔离层（160）以覆盖沟槽中有源区域的暴露边缘。 通过去除硬掩模和焊盘氧化层来暴露有源区域的边缘。 第一绝缘层形成在有源区的暴露边缘上。 在活性区域的暴露上侧形成第二绝缘层。 第二绝缘层比第一绝缘层薄。 导电图案形成在第一和第二绝缘层上。
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公开(公告)号：KR1020080002030A
公开(公告)日：2008-01-04
申请号：KR1020060060569
申请日：2006-06-30
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/42324 , H01L21/28273 , H01L29/66833
Abstract: A method for forming a gate structure of a non-volatile memory device is provided to improve a leakage current characteristic and a threshold voltage scattering of the non-volatile memory device by forming an interlayer dielectric made of a dual layer composed of a silicon oxide layer and a silicon oxynitride layer. A tunnel dielectric layer pattern(110a) and a floating gate(120a) are sequentially formed on a semiconductor substrate(100). An interlayer dielectric pattern(130a) is formed on the floating gate, and has a dual layer structure of a silicon oxide layer and a silicon oxynitride layer. A control gate(140a) is formed on the interlayer dielectric pattern. The silicon oxynitride layer is formed on the silicon oxide layer by an LPCVD(Low Pressure Chemical Vapor Deposition) process.
Abstract translation: 提供了一种用于形成非易失性存储器件的栅极结构的方法，用于通过形成由二氧化硅层构成的双层形成的层间电介质来改善非易失性存储器件的漏电流特性和阈值电压散射 和氮氧化硅层。 隧道介质层图案（110a）和浮动栅极（120a）依次形成在半导体衬底（100）上。 在浮置栅极上形成层间电介质图案（130a），并且具有氧化硅层和氮氧化硅层的双层结构。 在层间电介质图案上形成控制栅极（140a）。 通过LPCVD（低压化学气相沉积）工艺在氧化硅层上形成氧氮化硅层。
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公开(公告)号：KR100757335B1
公开(公告)日：2007-09-11
申请号：KR1020060101158
申请日：2006-10-18
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L29/7881 , H01L29/66825 , H01L21/28273 , H01L27/11521
Abstract: A non-volatile memory device and a method for fabricating the same are provided to ensure a sufficient interval between an active region and a control gate electrode and reduce an electrical disturbance therebetween. A tunnel insulating layer(120) is formed on an active region(100b) of a substrate. Field insulating patterns(126) are formed on a surface of the substrate to define the active region, and upper recesses(128) are formed on upper surfaces of the field insulating patterns. A stack structure consisting of a floating gate electrode, a blocking film and a control gate electrode is formed on the tunnel insulating layer. Impurity diffusion regions are formed around the active region.
Abstract translation: 提供了一种非易失性存储器件及其制造方法，以确保有源区域和控制栅电极之间的足够的间隔并减小它们之间的电气干扰。 在衬底的有源区（100b）上形成隧道绝缘层（120）。 场绝缘图案（126）形成在衬底的表面上以限定有源区，并且上凹部（128）形成在场绝缘图案的上表面上。 在隧道绝缘层上形成由浮栅电极，阻挡膜和控制栅电极构成的堆叠结构。 在活性区周围形成杂质扩散区。
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公开(公告)号：KR100745399B1
公开(公告)日：2007-08-02
申请号：KR1020060066204
申请日：2006-07-14
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115 , H01L21/31
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