-
公开(公告)号：KR1020110132125A
公开(公告)日：2011-12-07
申请号：KR1020100051963
申请日：2010-06-01
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/08 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L21/76829
Abstract: PURPOSE: A non-volatile memory device and a formation method thereof are provided to use an electrode made by including materials which are not a precious metal, thereby preventing contamination in manufacturing processes. CONSTITUTION: A gate pattern(13,14) is arranged on a semiconductor substrate(10). A contact plug(16) connected to a drain region(11) is provided in a first interlayer insulating film(15). A storage node(71) connected to the contact plug is provided on the first interlayer insulating film. The storage node comprises an electrode comprised of a lower electrode(20) and an upper electrode(60). A data storage layer(30) is placed between the lower electrode and upper electrode.
Abstract translation: 目的：提供一种非易失性存储器件及其形成方法，以使用通过包括不是贵金属的材料制成的电极，从而防止制造工艺中的污染。 构成：在半导体衬底（10）上布置栅极图案（13,14）。 连接到漏区（11）的接触插头（16）设置在第一层间绝缘膜（15）中。 连接到接触插头的存储节点（71）设置在第一层间绝缘膜上。 存储节点包括由下电极（20）和上电极（60）组成的电极。 数据存储层（30）被放置在下电极和上电极之间。
-
公开(公告)号：KR1020100007193A
公开(公告)日：2010-01-22
申请号：KR1020080067710
申请日：2008-07-11
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/06 , H01L21/02362 , H01L45/1233 , H01L45/143 , H01L45/144
Abstract: PURPOSE: A phase change memory device and a method for forming the same are provided to prevent damage to a phase change pattern in a patterning process after forming the phase change pattern by forming an upper electrode pattern and a conductive pattern with the same patterning process at the same time. CONSTITUTION: A bottom electrode(120) is formed on a semiconductor substrate(100). A phase change pattern(130) is electrically connected to the bottom electrode on the semiconductor substrate. A top electrode pattern(140) and a contact conductive pattern(150) are successively stacked. The phase change pattern, the top electrode pattern, and the contact conductive pattern are formed with the same patterning process as the same time. The side surfaces of the phase change pattern, the top electrode pattern, and the contact conductive pattern form the same plane.
Abstract translation: 目的：提供一种相变存储器件及其形成方法，以通过以相同的图案化工艺形成上电极图案和导电图案来防止在形成相变图案之后在图案化工艺中损坏相变图案 同一时间。 构成：在半导体衬底（100）上形成底电极（120）。 相变图案（130）电连接到半导体衬底上的底部电极。 依次层叠顶部电极图案（140）和接触导电图案（150）。 相变图案，顶部电极图案和接触导电图案以相同的图案化工艺形成。 相变图案，顶部电极图案和接触导电图案的侧表面形成相同的平面。
-
公开(公告)号：KR1020090107320A
公开(公告)日：2009-10-13
申请号：KR1020080032765
申请日：2008-04-08
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/143 , G11C13/0004 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1666 , H01L45/1683 , H01L45/141
Abstract: PURPOSE: A phase change memory device is provided to improve data retention by making a contact region small and reducing power consumption. CONSTITUTION: A phase change memory device is composed of a first electrode, a second electrode, a phase change material pattern(45), and a phase change assistant pattern(65). The phase change material pattern is interposed between the first electrode and the second electrodes, and the phase change assistant pattern contacts with a single-side of the phase change material pattern at least. The phase change assistant pattern includes a compound such as a chemical formula DaMb [GxTy] c: the formula is satisfied 0
Abstract translation: 目的：提供一种相变存储器件，通过使接触区域变小并降低功耗来提高数据保持性。 构成：相变存储装置由第一电极，第二电极，相变材料图案（45）和相变辅助图案（65）组成。 相变材料图案被插入在第一电极和第二电极之间，并且相变辅助图案至少与相变材料图案的单面接触。 相变助剂图案包括化合物如化学式DaMb [GxTy] c：满足公式0 <= a /（a + b + c）<= 0.20 <= b /（a + b + c） = 0.10.3 <= x /（x + y）<= 0.7。
-
公开(公告)号：KR1020080028653A
公开(公告)日：2008-04-01
申请号：KR1020060094217
申请日：2006-09-27
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L45/06 , C04B35/56 , C04B35/573 , C04B2235/3817 , C04B2235/3839 , C04B2235/3843 , C04B2235/40 , C04B2235/402 , C04B2235/404 , C04B2235/405 , C04B2235/408 , C04B2235/428 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675 , H01L45/1683
Abstract: A chalcogenide compound target, a method for forming the same, and a method for manufacturing a phase-change memory device are provided to increase a resistance and crystalline temperature of a phase change material layer by forming the phase change material layer with the same. A first powder including a germanium carbide or germanium is formed. A second powder including an antimony carbide or antimony is formed. A third powder including a tellurium carbide or tellurium is formed. The powder including the first, second, and third powders(S20) is mixed. The mixed powder is dried(S30). The mixed powder is sintered(S50).
Abstract translation: 提供硫属化物化合物靶，其形成方法和相变存储装置的制造方法，通过形成相变材料层来提高相变材料层的电阻和结晶温度。 形成包含碳化锗或锗的第一粉末。 形成包含锑化锑或锑的第二粉末。 形成包括碳化碲或碲的第三粉末。 混合包含第一，第二和第三粉末的粉末（S20）。 将混合粉末干燥（S30）。 将混合粉末烧结（S50）。
-
公开(公告)号：KR100784381B1
公开(公告)日：2007-12-11
申请号：KR1020040057760
申请日：2004-07-23
Applicant: 삼성전자주식회사
IPC: H01L21/205
CPC classification number: C23C14/165 , C23C14/046 , C23C14/35 , C23C14/50
Abstract: 본 발명은 GST막과 같은 상변화 물질막을 웨이퍼에 증착하는 장치로, 상기 장치는 기판 지지부, 타겟, 그리고 자석 부재가 설치된 공정 챔버를 가진다. 기판 지지부는 웨이퍼를 기구적인 방법으로 지지하며, 기판과 접촉되는 부분은 질화 알루미늄을 재질로 하여 이루어진다. 상술한 구조로 인해 웨이퍼 상에서 불균일한 필드가 형성되는 것이 방지되며, 웨이퍼의 전체 영역에서 증착 두께와 증착 물질의 조성비가 균일하다.
GST, 스퍼터, 타겟, 고정부재, 상변화 물질막Abstract translation: 用于在衬底上沉积薄膜的装置包括壳体，衬底支撑部分，固定构件，加热器，目标构件和等离子体发生器。 壳体限定了处理室。 衬底支撑部分设置在处理室中以支撑衬底。 固定构件适于在执行过程期间将基板非电气地固定到基板支撑部分。 提供加热器以将基板支撑部分支撑的基板保持在处理温度。 目标构件面向衬底支撑部分并且包括待沉积在衬底上的材料。 等离子体发生器适于将供应到处理室中的处理气体激发成等离子体状态。
-
Patent Agency Ranking
公开(公告)号：KR100674972B1
公开(公告)日：2007-01-29
申请号：KR1020050043812
申请日：2005-05-24
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R31/2601
Abstract: 반도체 소자의 펄스 특성을 측정할 수 있는 측정 시스템 및 측정 방법이 제공된다. 본 발명에 따른 측정 시스템은, 반도체 소자의 단자들에 전기적 접촉이 가능한 적어도 한 쌍의 제 1 및 제 2 프로브들과, 제 1 프로브에 연결되고 펄스 신호를 출력할 수 있는 펄스 발생기와, 적어도 한 쌍의 제 1 및 제 2 채널들을 갖고, 제 1 채널은 펄스 전원을 제 1 프로브와 병렬로 공급받을 수 있고, 제 2 채널은 제 2 프로브에 연결될 수 있는 오실로스코프를 포함한다. 오실로스코프는 제 2 채널을 이용하여 반도체 저항 소자의 단자들을 흐르는 펄스 전류를 계산하고, 제 1 및 제 2 채널들을 이용하여 반도체 저항 소자의 다이나믹 저항을 측정한다.
-
公开(公告)号：KR102238444B1
公开(公告)日：2021-04-09
申请号：KR1020170031294
申请日：2017-03-13
Applicant: 삼성전자주식회사
IPC: H01L27/088 , H01L21/8234
Abstract: 반도체장치및 그제조방법이제공된다. 반도체장치는, 제1 및제2 영역을포함하는기판, 제1 영역의기판상에배치되는제1 인터페이스막, 제2 영역의기판상에배치되는제2 인터페이스막, 제1 및제2 인터페이스막상에배치되는유전막, 제1 영역의유전막상에배치되는제1 금속막, 및제2 영역의유전막상에배치되는제2 금속막을포함하고, 제1 및제2 인터페이스막은기판의산화물을포함하고, 제1 및제2 금속막은서로다른물질을포함하고, 제1 및제2 인터페이스막은서로다른두께를갖는다.
-
公开(公告)号：KR1020110091844A
公开(公告)日：2011-08-16
申请号：KR1020110072893
申请日：2011-07-22
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115 , H01L21/203
CPC classification number: H01L45/1625 , C23C14/3414 , G11B7/00454 , G11B7/243 , G11B2007/2431 , G11B2007/24312 , G11B2007/24314 , G11B2007/24328 , H01L45/06 , H01L45/144 , H01L45/143
Abstract: PURPOSE: A phase change recording layer with high electric resistance and a sputtering target for forming the same are provided to reduce the property of a phase change type nonvolatile memory layer and reduce manufacturing costs by reducing a current in a record erasing operation. CONSTITUTION: A phase change recording layer has a variable electric resistance property. The phase change recording layer includes Ge of 17 to 25%, Sb of 17 to 25%, and C of 0.5 to 6%. The rest of the phase change recording layer is made of Te and impurities. The resistivity of the phase change recording layer by is 5 x 10^-2 to 5 x 10^1 Ω Cm.
Abstract translation: 目的：提供一种具有高电阻的相变记录层和用于形成其的溅射靶，以降低相变型非易失性存储层的性能，并且通过减少记录擦除操作中的电流来降低制造成本。 构成：相变记录层具有可变的电阻特性。 相变记录层的Ge为17〜25％，Sb为17〜25％，C为0.5〜6％。 相变记录层的其余部分由Te和杂质构成。 相变记录层的电阻率为5×10 ^ -2至5×10 ^ 1ΩCm。
-
公开(公告)号：KR1020110000961A
公开(公告)日：2011-01-06
申请号：KR1020090058316
申请日：2009-06-29
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1683
Abstract: PURPOSE: A nonvolatile memory device is provided to prevent the formation of a void due to the oxidation of a phase change material layer and etching non-uniformity by forming a phase change material layer into a multilayer before and after a node separation process. CONSTITUTION: A first phase change material layer(150) is formed on a lower electrode(130). A gate structure(110) is formed on a substrate(100). The gate structure comprises a gate isolation layer(102) and a gate electrode layer(104). A second phase change material layer(170) is located to be electrically connected to the first phase change material layer. An upper electrode(180) is located on the second phase change material layer in order to be electrically connected to.
Abstract translation: 目的：提供一种非易失性存储器件，以防止由于相变材料层的氧化而形成空隙，并且通过在节点分离工艺之前和之后将相变材料层形成为多层而蚀刻不均匀。 构成：在下电极（130）上形成第一相变材料层（150）。 栅极结构（110）形成在衬底（100）上。 栅极结构包括栅极隔离层（102）和栅极电极层（104）。 第二相变材料层（170）被定位成电连接到第一相变材料层。 上电极（180）位于第二相变材料层上以便电连接。
-
公开(公告)号：KR1020100055102A
公开(公告)日：2010-05-26
申请号：KR1020080114028
申请日：2008-11-17
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1683 , H01L21/31051 , H01L21/76224
Abstract: PURPOSE: A variable resistance memory device, a manufacturing method thereof, and a memory system including the same are provided to improve an operation property of a variable resistance material by etching the variable resistance material after etching the variable resistance material. CONSTITUTION: An interlayer insulation layer including trenches is formed on lower electrodes(227). A variable resistance material(235) is formed on the interlayer insulation layer and the trenches. A planarization process is performed on the variable resistance material to expose the upper side of the interlayer insulation layer. A contamination material(237) is removed on the variable resistance material inside the trenches by etching the variable resistance material inside the trenches. An upper electrode is formed on the variable resistance pattern.
Abstract translation: 目的：提供可变电阻存储器件及其制造方法以及包括该可变电阻存储器件的存储器系统，以在蚀刻可变电阻材料之后蚀刻可变电阻材料来改善可变电阻材料的操作特性。 构成：在下电极（227）上形成包括沟槽的层间绝缘层。 在层间绝缘层和沟槽上形成可变电阻材料（235）。 对可变电阻材料进行平坦化处理以暴露层间绝缘层的上侧。 通过蚀刻沟槽内的可变电阻材料，在沟槽内的可变电阻材料上去除污染物质（237）。 在可变电阻图案上形成上电极。
-
-
-
-
-
-
-
-
-
Search Results
53
records
(took 0.023 seconds)
