-
-
公开(公告)号：KR1019920000480B1
公开(公告)日：1992-01-14
申请号：KR1019890019308
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/32
Abstract: The method is to support interprocess communication of multiprocessor system. When an interrupt request signal is received, arbiters are drived fromthe first bit according to thepriorities to allow the usage of interrupt bus for processors. The circuit includes an interrupt requester (5) for request arbitration to interrupt handlers (3,4) when the interrupt request signal from processors (1,2) is received, interrupt handlers (3,4) for processing the arbitration request and interrupts occured in boards in which processors are deposited, an interrupt arbiter (7) for executing the arbitration and sending the result to the interrupt requestor (5), and for arbitrating the interrupt handlers, and an interrupt bus synchronizing signal (IBSYNC) driver (8) for generating the IBSYNC signal to drive the signal line (9) and for sending the IBSYNC signal to the interrupt requester (5).
Abstract translation: 该方法是支持多处理器系统的进程间通信。 当接收到中断请求信号时，根据优先级从第一位驱动仲裁器，以允许对处理器使用中断总线。 当接收到来自处理器（1,2）的中断请求信号时，该电路包括用于请求仲裁以中断处理程序（3,4）的中断请求器（5），用于处理仲裁请求的中断处理程序（3,4） 在处理器存放的板中，执行仲裁并将结果发送给中断请求者（5）并用于仲裁中断处理程序的中断仲裁器（7）和中断总线同步信号（IBSYNC）驱动器（8） 用于产生IBSYNC信号以驱动信号线（9）并将IBSYNC信号发送到中断请求器（5）。
-
-
-
公开(公告)号：KR1019960001092B1
公开(公告)日：1996-01-18
申请号：KR1019930024330
申请日：1993-11-16
Applicant: 한국전자통신연구원
IPC: G06F1/06
Abstract: initializing a timer; repeating the above operation until a raising edge by checking the raising edge; checking a value of a CCR when a clock is at the raising edge; in case of a value "0", copying a MCR on the CCR; in case that the CCR is not 0" and a BCR is not "0", checking whether the BCR is "0" or not; in case that the CCR is "1" and the BCR is "0", copying the MCR on the CCR, and the MCR on the BCR; checking whether the CCR is not "1" and whether the BCR is "0"; in case that the BCR is "0", reducing the CCR by 1, copying it on the BCR; and in case that the BCR is not "0", reducing the value of the BCR by 1.
Abstract translation: 初始化一个定时器; 通过检查提升边缘重复上述操作直到升起边缘; 当时钟处于上升沿时检查CCR的值; 在值“0”的情况下，复制CCR上的MCR; 在CCR不为0“且BCR不为”0“的情况下，检查BCR是否为”0“;如果CCR为”1“且BCR为”0“，则复制MCR CCR和BCR上的MCR;检查CCR是否不是“1”，以及BCR是否为“0”;如果BCR为“0”，则将CCR减少1，将其复制到BCR上; 并且在BCR不为“0”的情况下，将BCR的值减小1。
-
Patent Agency Ranking
-
公开(公告)号：KR1019940009704B1
公开(公告)日：1994-10-17
申请号：KR1019910023200
申请日：1991-12-17
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The method prevents the delay of the data response of the read operation when the read and write operations use one data bus simultaneously on the pended protocol adapting to the highly pipelined bus. When the address data unit period and the data unit period request the data bus simultaneously and then the usage of the data bus for the data unit period is cancelled, the data bus arbitration request signal is provided if the data bus arbitration request signal is driving, or the write operation signal is "true" under conditions that the data bus is enable and the arbitration is requested.
Abstract translation: 当读写操作在适应高流水线总线的挂起协议上同时使用一个数据总线时，该方法可以防止读操作的数据响应延迟。 当地址数据单元周期和数据单元周期同时请求数据总线，然后消除数据单元周期的数据总线的使用时，如果数据总线仲裁请求信号正在驱动，则提供数据总线仲裁请求信号， 或者在数据总线使能和请求仲裁的条件下，写操作信号为“真”。
-
公开(公告)号：KR1019940015822A
公开(公告)日：1994-07-21
申请号：KR1019920026633
申请日：1992-12-30
Applicant: 한국전자통신연구원
IPC: G06F11/08
Abstract: 본 발명은 다중 프로세서 시스템에서 복수의 캐쉬 메모리 모듈(2a∼2n)이 존재할때 이들의 복잡한 상태천이동작을 효과적으로 시험하여 오류의 장소 및 시기등의 정보를 얻기 용이하게 하는 것으로, 복수의 캐쉬 메모리 모듈(2a∼2n)의 상태 변화가능의 경우를 분류하여 각 경우에 대한 시험방법을 제시함으로써 효과적으로 오류를 발견할 수 있도록 해준다.
-
公开(公告)号：KR1019940005778B1
公开(公告)日：1994-06-23
申请号：KR1019910025587
申请日：1991-12-31
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The access arbitrating circuit includes a program device for generating combination signals, an AND gate, a first register synchronized with the output signal of the AND gate, a second register synchronized with a clock pulse, a comparator for comparing the output signals of the first and second registers, a first flip-flop synchronized with a delayed clock pulse, a second flip-flop for generating a signal enabling the comparator, an OR gate, and a third flip-flop synchronized with the delayed clock pulse, thereby improving the performance of a system.
Abstract translation: 访问仲裁电路包括用于产生组合信号的编程装置，与门，与AND门的输出信号同步的第一寄存器，与时钟脉冲同步的第二寄存器，比较器，用于比较第一和 第二寄存器，与延迟时钟脉冲同步的第一触发器，用于产生使能比较器的信号的第二触发器，或与延迟时钟脉冲同步的OR门和第三触发器，由此提高 一个系统。
-
公开(公告)号：KR1019940005777B1
公开(公告)日：1994-06-23
申请号：KR1019910025367
申请日：1991-12-30
Applicant: 한국전자통신연구원
IPC: G06F12/08
Abstract: The circuit for varying a cache directory using first-in first-out (FIFO) includes a program device for generating combination signals, a FIFO for storing a bus address, first and second AND gates, and a flip-flop synchronized with a clock signal, thereby simplifying a circuit construction.
Abstract translation: 用于使用先进先出（FIFO）改变高速缓存目录的电路包括用于产生组合信号的程序设备，用于存储总线地址的FIFO，第一和第二与门以及与时钟信号同步的触发器 ，从而简化电路结构。
-
-
-
-
-
-
-
-
-
Search Results
143
records
(took 0.019 seconds)
