公开(公告)号：AU2014349165B2

公开(公告)日：2017-04-13

申请号：AU2014349165

申请日：2014-09-26

Applicant: APPLE INC

Inventor： SILVERSTEIN D AMNON ,  GO SHUN WAI ,  LIM SUK HWAN ,  MILLET TIMOTHY J ,  CHEN TING ,  NI BIN

IPC: H04N7/01 ,  H04N5/232

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4x3 aspect ratio and at higher resolution than the 16x9 aspect ratio video frames. The device may interleave high resolution, 4x3 frames and lower resolution 16x9 frames in the video sequence, and may capture the nearest higher resolution, 4x3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16x9 frames in the video sequence, and then expand to 4x3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16x9 video frames responsive to a release of the shutter button.

公开(公告)号：BR112012017007A2

公开(公告)日：2016-04-05

申请号：BR112012017007

申请日：2011-01-05

Applicant: APPLE INC

Inventor： BRATT JOSEPH P ,  HOLLAND PETER F ,  CHOO SHING HORNG ,  MILLET TIMOTHY J

IPC: G06F3/14 ,  H04N5/265

Abstract: uniade de interface de usuário para busca apenas de regiões ativas em um quadro. a presente invenção refere-se a uma unidade de interface de usuário em um tubo de exibição de processamento de itens gráficos, que pode incluir registradores programáveis com uma informação que define regiões ativas de um quadro de imagem. os pixels nas regiões ativas do quadro de imagem têm por propósito serem exibidos, enquanto os pixels fora das regiões ativas do quadro de imagem não são para serem exibidos. um circuito de busca na unidade de interface de usuário pode buscar quadros a partir da memória; buscando apenas os pixels nas regiões ativas dos quadros de imagem, conforme definido conteúdos programados dos registradores. a unidade de interface de usuário então pode prover os pixels buscados para uma unidade de mescla para mescla dos pixels buscados com piexls de outros quadros ou pixels de fluxo de vídeo para a produção de quadros de saída. quando mesclados com pixels de um fluxo de vídeo, os pixels buscados podem ser exibidos como uma superposição de itens gráficos no topo do fluxo de vídeo.

公开(公告)号：GB2498416B

公开(公告)日：2013-11-06

申请号：GB201212303

申请日：2011-01-05

Applicant: APPLE INC

Inventor： BRATT JOSEPH P ,  CHOO SHING HORNG ,  HOLLAND PETER F ,  MILLET TIMOTHY J

IPC: H04N5/265 ,  G06F3/14 ,  G06T1/20

Abstract: A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.

公开(公告)号：HK1181230A1

公开(公告)日：2013-11-01

申请号：HK13108492

申请日：2013-07-19

Applicant: APPLE INC

Inventor： BRATT JOSEPH P ,  CHOO SHING HORNG ,  HOLLAND PETER F ,  MILLET TIMOTHY J

IPC: H04N20060101 ,  G06F20060101 ,  G06T20060101

Abstract: A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.

公开(公告)号：AU2011237758B2

公开(公告)日：2013-10-03

申请号：AU2011237758

申请日：2011-04-06

Applicant: APPLE INC

Inventor： DE CESARE JOSH ,  CHO JUNG WOOK ,  TAKAYANAGI TOSHI ,  MILLET TIMOTHY J

IPC: G06F1/00

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

公开(公告)号：BR102012024573A2

公开(公告)日：2013-09-03

申请号：BR102012024573

申请日：2012-09-27

Applicant: APPLE INC

Inventor： TRIPATH BRIJESH ,  MILLET TIMOTHY J

IPC: H03L7/06

Abstract: A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface.

公开(公告)号：MX2012011619A

公开(公告)日：2012-11-30

申请号：MX2012011619

申请日：2011-04-06

Applicant: APPLE INC

Inventor： CESARE JOSH DE ,  CHO JUNG WOOK ,  TAKAYANAGI TOSHI ,  MILLET TIMOTHY J

IPC: G06F1/00

Abstract: En una modalidad, una unidad de administración de energía (PMU) puede transitar automáticamente (en el hardware) los estados de rendimiento de uno o más dominios de rendimiento en un sistema. Los estados de rendimiento objetivo a los cuales los dominios de rendimiento deben transitar pueden ser programables en la PMU por el software, y el software puede indicar a la PMU que un procesador en el sistema debe entrar al estado de reposo. La PMU puede controlar la transición de los dominios de rendimiento a los estados de rendimiento objetivo, y puede ocasionar que el procesador entre al estado de reposo. En una modalidad, la PMU puede ser programable con un segundo conjunto de estados de rendimiento objetivo a los cuales los dominios de rendimiento deben transitar cuando el procesador sale del estado de reposo. La PMU puede controlar la transición de los dominios de rendimiento a los segundos estados de rendimiento objetivo, y ocasionar que el procesador salga del estado de reposo.

公开(公告)号：NL2007481A

公开(公告)日：2012-04-02

申请号：NL2007481

申请日：2011-09-27

Applicant: APPLE INC

Inventor： MILLET TIMOTHY J ,  MACHNICKI ERIC P ,  BALKAN DENIZ ,  GUPTA VIJAY

IPC: G06F1/32

Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

公开(公告)号：DE112015004438B4

公开(公告)日：2022-06-23

申请号：DE112015004438

申请日：2015-08-17

Applicant: APPLE INC

Inventor： GULATI MANU ,  MACHNICKI ERIK P ,  COX KEITH ,  MILLET TIMOTHY J ,  DE LA CROPTE DE CHANTERAC CYRIL

IPC: G06F1/32 ,  G06F1/3206

Abstract: System (100), umfassend:eine oder mehrere Funktionseinheiten, wobei mindestens eine Funktionseinheit der einen oder mehreren Funktionseinheiten mindestens eine Monitorschaltung (107a) einschließt, wobei die mindestens eine Monitorschaltung (107a) konfiguriert ist zum:Überwachen (302) eines Betriebsparameters, der einer dazugehörigen Funktionseinheit (102) zugeordnet ist; undSenden von Daten, die den Betriebsparameter angeben; undeinen Stromverwalter-Prozessor (106), der mit einem flüchtigen Speicher gekoppelt ist, wobei der dedizierte Stromverwalter-Prozessor (106) konfiguriert ist zum:Empfangen der Daten;Anpassen (307) von einer oder mehreren Leistungseinstellungen in Abhängigkeit von den Daten; undum als Reaktion auf ein Empfangen eines durch die mindestens eine Monitorschaltung (107a) erzeugten Interrupts einen Niedrigenergiemodus zu verlassen.

公开(公告)号：DE112015002522B4

公开(公告)日：2022-05-25

申请号：DE112015002522

申请日：2015-03-13

Applicant: APPLE INC

Inventor： TRIPATHI BRIJESH ,  KEIL SHANE ,  GULATI MANU ,  CHO JUNG WOOK ,  MACHNICKI ERIK P ,  HERBECK GILBERT H ,  MILLET TIMOTHY J ,  CESARE JOSHUA P DE ,  DALAL ANAND

IPC: G06F1/30 ,  G06F1/32

Abstract: Integrierte Schaltung (10), umfassend:mindestens einen Prozessor (30), der eine Zentraleinheit in der integrierten Schaltung (10) bildet;eine Energieverwaltungsschaltung (32), konfiguriert zum Übertragen von Spannungsanforderungen an eine Energieverwaltungseinheit (156), die extern zur integrierten Schaltung (10) ist, wobei die Spannungsanforderungen Anforderungen sind, um eine oder mehrere Stromversorgungsspannungen zur integrierten Schaltung (10) zu leiten;einen Speicher-Controller (22), gekoppelt mit einem Speicher (12) während des Betriebs, wobei die Energieverwaltungsschaltung (32) konfiguriert ist, um ein Herunterfahren des Speicher-Controllers (22) über eine Kommunikation mit der Energieverwaltungseinheit (156) zu veranlassen; undeine erste, mit dem Prozessor (30) und dem Speicher-Controller (22) gekoppelte Komponente (16), wobei die erste Komponente (16) konfiguriert ist, um eingeschaltet zu bleiben, während der Prozessor (30), die Energieverwaltungsschaltung (32) und der Speicher-Controller (22) abgeschaltet sind, und wobei die erste Komponente (16) separat von der Energieverwaltungsschaltung (32) mit der Energieverwaltungseinheit (156) gekoppelt ist, und wobei die erste Komponente (16) konfiguriert ist, um das Hochfahren des Speicher-Controllers (22) über die separate Kopplung mit der Energieverwaltungseinheit (156) zu veranlassen, um den Speicher-Controller (22) unter Verwendung der in der ersten Komponente (16) gespeicherten Konfigurationsdaten des Speicher-Controllers (22) zu programmieren und um mit dem Speicher-Controller (22) während einer Zeit, in der der Prozessor (30) heruntergefahren ist, zu kommunizieren.