公开(公告)号：IT9006609D0

公开(公告)日：1990-04-20

申请号：IT660990

申请日：1990-04-20

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/78 ,  H01L

Abstract: The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage in comparison with known structures by provision of one or more regions of high dopant concentration defined after growth of a first epitaxial layer.

公开(公告)号：DE69427913D1

公开(公告)日：2001-09-13

申请号：DE69427913

申请日：1994-10-28

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  FALLICO GIUSEPPE

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/423 ,  H01L29/732

公开(公告)号：DE69327320D1

公开(公告)日：2000-01-20

申请号：DE69327320

申请日：1993-09-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78

Abstract: An integrated structure active clamp for the protection of a power device against overvoltages comprises a plurality of serially connected diodes (D1-D4,SD1-D4,DF1,DF2), each having a first and a second electrodes, obtained in a lightly doped epitaxial layer (2;2,2') of a first conductivity type in which the power device (M) is also obtained; a first diode (D1;SD1) of said plurality of diodes has the first electrode (12,13;31,32) connected to a gate layer (7) of the power device (M) and the second electrode (14,15;35) connected to the second electrode (16,17;21,22;27,52,28) of at least one second diode (D2-D4) of the plurality whose first electrode (18,20,24,29) is connected to a drain region (D) of the power device (M); said first diode (D1;SD1) has its first electrode (12,13;31,32) comprising a heavily doped contact region (12;32) of the first conductivity type included in a lightly doped epitaxial layer region (13;31) of the first conductivity type which is isolated from said lightly doped epitaxial layer (2;2,2') by means of a buried region (14;33) of a second conductivity type and by a heavily doped annular region (15;34) of the second conductivity type extending from a semiconductor top surface to said buried region (14;33).

公开(公告)号：DE69029942T2

公开(公告)日：1997-08-28

申请号：DE69029942

申请日：1990-10-16

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  MAGRO CARMELO

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/772

Abstract: The process provides first for the accomplishment of low-doping body regions (12) at the sides and under a gate region (15) and then the accomplishment of high-doping body regions (14) inside said low-doping body regions (12) and self-aligned with said gate region (15). There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions (14) self-aligned with said gate region (15) and with a reduced junction depth.

公开(公告)号：DE69125390D1

公开(公告)日：1997-04-30

申请号：DE69125390

申请日：1991-07-03

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L27/06 ,  H01L21/331 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732

公开(公告)号：DE69113987D1

公开(公告)日：1995-11-23

申请号：DE69113987

申请日：1991-04-17

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73

公开(公告)号：IT9022577A1

公开(公告)日：1992-07-01

申请号：IT2257790

申请日：1990-12-31

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： PAPARO MARIO ,  PUZZOLO SANTO ,  ZAMBRANO RAFFAELE

IPC: H01L21/8249 ,  H01L20060101 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732

公开(公告)号：ITMI913267D0

公开(公告)日：1991-12-05

申请号：ITMI913267

申请日：1991-12-05

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78

公开(公告)号：IT9006610D0

公开(公告)日：1990-05-31

申请号：IT661090

申请日：1990-05-31

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE ,  GRIMALDI GIUSEPPE

IPC: H01L21/8249 ,  H01L21/76 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78

Abstract: By using a diffused insulation region placed around the body region and with deeper junction and hence longer curvature radius than the typical body/drain junction values, in combination with an appropriate layout of the buried drain region underneath the power stage, breakdown voltage is maximized without compromising the Ron series resistance of the power stage and the reliability of the device.

公开(公告)号：DE69432407D1

公开(公告)日：2003-05-08

申请号：DE69432407

申请日：1994-05-19

Applicant: CONS RIC MICROELETTRONICA

Inventor： ZAMBRANO RAFFAELE

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/76 ,  H01L27/088 ,  H01L29/78 ,  H01L29/72

Abstract: A Power Integrated Circuit ("PIC") structure comprises a lightly doped semiconductor layer (2;2',2'') of the first conductivity type superimposed over a heavily doped semiconductor substrate (3) of a second conductivity type, wherein a Vertical IGBT and a driving and control circuitry comprising at least first conductivity type-channel MOSFETs are integrated; the MOSFETs are obtained inside well regions (15) of the second conductivity type which are included in at least one lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer (2;2',2'') of the first conductivity type by means of a respective isolated region (12,13) of a second conductivity type.