公开(公告)号：EP0817058A2

公开(公告)日：1998-01-07

申请号：EP97303792.2

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  Culley, Paul R.

IPC: G06F11/34

CPC classification number: G06F11/349 ,  G06F11/3495

Abstract: Performance of a bus in a computer system is monitored. A predetermined total period is counted, and usage of the bus for data transfers during the total period is measured. The bus is monitored for active cycles and a period is counted in which the active cycles are present during the total period. The bus is monitored for data transfer cycles and a period is counted in which the data transfer cycles are present during the total period. Bus efficiency is measured based on the active period and data transfer period. Read data usage on the bus is also measured. A first amount of data read by a first device is monitored, and a second amount of read data used by a second bus device is monitored. The read efficiency is determined based on the first and second amounts.

Abstract translation: 监控计算机系统中总线的性能。 对预定的总时段进行计数，并且测量在总时段期间用于数据传输的总线的使用。 监视总线的有效周期，并计算在整个周期内存在有效周期的周期。 监视总线进行数据传输周期，并计算在整个周期内存在数据传输周期的周期。 总线效率是根据活动期和数据传输周期来测量的。 也读取总线上的数据使用情况。 监视由第一设备读取的第一数据量，并且监视由第二总线设备使用的第二数量的读取数据。 基于第一和第二量确定读取效率。

公开(公告)号：EP0817055A2

公开(公告)日：1998-01-07

申请号：EP97303800.3

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  Sides, Chi Kim ,  Miller, Joseph P. ,  Cox, Tod B. ,  Cook, M. Damian ,  Sanders, Michael C.

IPC: G06F11/20

CPC classification number: G06F11/2025 ,  G06F11/0757 ,  G06F11/142 ,  G06F11/2002 ,  G06F11/2023 ,  G06F11/2028 ,  G06F11/2033 ,  G06F11/2038 ,  G06F11/2046 ,  G06F11/22 ,  G06F13/4022

Abstract: Control is switched from a first server to a second server in a fault tolerant system. The first and second servers are coupled with an expansion bus in an expansion box for communication with the expansion bus. An indication is provided to the second server to indicate the activity state of the first server. Communication between the first server and the expansion box is disabled if the indication indicates the first server is inactive. Communication between the second server and the expansion bus is disabled if the indication indicates that the first server is active. Communication between the second server is enabled if the indication indicates that the first server is inactive. The indication includes a heartbeat message transmitted periodically to the second server. The expansion bus includes a PCI bus.

Abstract translation: 控制从容错系统中的第一个服务器切换到第二个服务器。 第一和第二服务器与用于与扩展总线通信的扩展盒中的扩展总线连接。 向第二服务器提供指示以指示第一服务器的活动状态。 如果指示表明第一台服务器处于非活动状态，则第一台服务器和扩展盒之间的通信将被禁用。 如果指示表明第一台服务器处于活动状态，则第二台服务器和扩展总线之间的通信将被禁用。 如果该指示指示第一服务器不活动，则启用第二服务器之间的通信。 该指示包括周期性发送给第二服务器的心跳消息。 扩展总线包括一个PCI总线。

公开(公告)号：EP0811938A2

公开(公告)日：1997-12-10

申请号：EP97303807.8

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Whiteman, William F. ,  Goodrum, Alan L. ,  Cox, Tod B. ,  Basile, Barry S.

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/404

Abstract: A computer system has a central processing unit and a bus. A first bus device and a second bus device are connected to the bus. A circuit is connected to configure the second bus device to be addressable by the central processing unit via the bus only by interaction with the first bus device. The first bus device may be an I 2 O processor, and the second bus device may be an I 2 O subordinate bus device.

Abstract translation: 计算机系统具有中央处理单元和总线。 第一总线设备和第二总线设备连接到总线。 电路被连接以通过总线仅通过与第一总线设备的交互来将第二总线设备配置为可由中央处理单元寻址。 第一总线设备可以是I2O处理器，并且第二总线设备可以是I2O从属总线设备。

公开(公告)号：EP0811924A2

公开(公告)日：1997-12-10

申请号：EP97303799.7

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Ramsey, Jens K. ,  Goodrum, Alan L. ,  Culley, Paul R.

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: Access to a bus in a computer system having a CPU and bus devices capable of running cycles on a bus is controlled by an arbiter. The arbiter grants access to the bus according to an arbitration scheme that depends on whether a request for the bus is pending from the CPU, in which a first arbitration scheme arbitrates between the bus devices, and wherein a second arbitration scheme arbitrates between the CPU and at least one other bus device if the CPU request is present.

Abstract translation: 具有能够在总线上运行周期的CPU和总线设备的计算机系统中的总线的访问由仲裁器控制。 仲裁器根据仲裁方案授权对总线的访问，该仲裁方案取决于来自CPU的总线请求是否等待，其中第一仲裁方案在总线设备之间进行仲裁，并且其中第二仲裁方案在CPU和 如果存在CPU请求，则至少另外一个总线设备。

公开(公告)号：EP0426183A3

公开(公告)日：1992-12-23

申请号：EP90120980.9

申请日：1990-11-02

Applicant: Compaq Computer Corporation

Inventor： Melo, Maria L. ,  Landry, John A. ,  Culley, Paul R. ,  Goodrum, Alan L.

IPC: G06F13/42

CPC classification number: G06F13/4018 ,  G06F13/26 ,  G06F13/362 ,  G06F13/4072 ,  G06F13/409 ,  G06F13/423

Abstract: An apparatus for use in a computer system which delays operation when a wait signal is present, the apparatus providing a delay between back-to-back input/output cycles, the apparatus comprising: means for storing a programmed value that represents the length of delay to be provided between said back-to-back input/output cycles; means coupled to said storing means for producing a signal representing said length of delay; and means receiving said length of delay signal for generating the wait signal that delays the start of a successive inpt/output cycle for the length of time of said programmed delay.

Abstract translation: 一种在计算机系统中使用的装置，其在等待信号存在时延迟操作，所述装置在背靠背输入/输出周期之间提供延迟，所述装置包括：用于存储表示延迟长度的编程值的装置 在所述背对背输入/输出周期之间提供; 耦合到所述存储装置的装置，用于产生表示所述延迟长度的信号; 并且装置接收所述延迟信号的长度，用于产生延迟所述编程延迟的时间长度的连续输入/输出周期开始的等待信号。

公开(公告)号：EP0382358A2

公开(公告)日：1990-08-16

申请号：EP90300601.3

申请日：1990-01-19

Applicant: Compaq Computer Corporation

Inventor： Wanner, Christopher C. ,  Goodrum, Alan L. ,  Culley, Paul R.

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F12/0835

Abstract: The computer system disclosed includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DMA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.

Abstract translation: 游离缺失的计算机系统盘包括直接存储器存取（DMA）控制器，它可提供一个32位存储器地址，但这样可以提供24位存储器地址操作保持与以前的系统兼容。 DMA控制器从而监视系统的操作，并且如果只有24比特的地址的操作的外部总线主机或DMA控制器的控制下发生的，DMA控制器驱动提供给高速缓冲存储器控制器的顶部存储器地址字节，以帮助保证高速缓存相关性。 此外，DMA控制器可以为奇数起始存储器地址之间的字宽传送提供最佳的时间传输，并甚至起始输入/输出端口。

公开(公告)号：EP0821310B1

公开(公告)日：2004-12-15

申请号：EP97303795.5

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  MacLaren, John M. ,  Pettey, Christopher J. ,  Culley, Paul R.

IPC: G06F13/364 ,  G06F13/40

CPC classification number: G06F13/364 ,  G06F13/4054

公开(公告)号：EP0817058B1

公开(公告)日：2003-08-13

申请号：EP97303792.2

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L. ,  Culley, Paul R.

IPC: G06F11/34

CPC classification number: G06F11/349 ,  G06F11/3495

Abstract: Performance of a bus in a computer system is monitored. A predetermined total period is counted, and usage of the bus for data transfers during the total period is measured. The bus is monitored for active cycles and a period is counted in which the active cycles are present during the total period. The bus is monitored for data transfer cycles and a period is counted in which the data transfer cycles are present during the total period. Bus efficiency is measured based on the active period and data transfer period. Read data usage on the bus is also measured. A first amount of data read by a first device is monitored, and a second amount of read data used by a second bus device is monitored. The read efficiency is determined based on the first and second amounts.

公开(公告)号：EP0811931B1

公开(公告)日：2003-05-02

申请号：EP97303797.1

申请日：1997-06-04

Applicant: Compaq Computer Corporation

Inventor： Culley, Paul R. ,  Goodrum, Alan L. ,  Chow, Raymond Y. L. ,  Basile, Barry S.

IPC: G06F13/40

CPC classification number: G06F13/4081

公开(公告)号：EP0851362B1

公开(公告)日：2003-04-23

申请号：EP97310692.5

申请日：1997-12-31

Applicant: Compaq Computer Corporation

Inventor： Goodrum, Alan L.

IPC: G06F13/40

CPC classification number: G06F13/4059