中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

54 records (took 0.017 seconds)

    22.
    发明专利
    未知

    公开(公告)号：AT334520T

    公开(公告)日：2006-08-15

    申请号：AT02747299

    申请日：2002-05-03

    Applicant: IBM

    Inventor： BARKER KENNETH JAMES ,  CLAUBERG ROLF ,  CALVIGNAC JEAN LOUIS ,  HERKERSDORF ANDREAS GUENTHER ,  VERPLANKEN FABRICE JEAN ,  WEBB DAVID JOHN

    IPC: H04J3/00 ,  H04J3/06 ,  H04J3/16 ,  H04J3/22 ,  H04L13/08 ,  H04Q11/04 ,  H04J3/04

    Abstract: The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.

    23.
    发明专利
    未知

    公开(公告)号：AT291802T

    公开(公告)日：2005-04-15

    申请号：AT02715591

    申请日：2002-01-28

    Applicant: IBM

    Inventor： BASSO CLAUDE ,  CALVIGNAC JEAN LOUIS ,  HEDDES MARCO ,  LOGAN JOSEPH FRANKLIN ,  VERPLANKEN FABRICE JEAN

    IPC: H04L12/18 ,  H04L12/56

    Abstract: Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.

    24.
    发明专利
    未知

    公开(公告)号：BR0214890A

    公开(公告)日：2004-12-14

    申请号：BR0214890

    申请日：2002-12-09

    Applicant: IBM

    Inventor： CALVIGNAC JEAN LOUIS ,  VERPLANKEN FABRICE JEAN

    IPC: H04L12/56 ,  G06F17/30 ,  H04L12/46

    Abstract: A system includes a data structure having a Direct Table (DT), Patricia-Trees, Pointers and high speed storage systems such as Contents Address Memory (CAM). The DT has a plurality of entries with each one coupled to a Patricia Tree having multiple nodes coupled to leaves. The number of Nodes, termed a threshold, that can be traversed to obtain information in the leaves is limited to a predetermined value. Once the threshold is reached a pointer indicates the address of the CAM and the address of the leaves is stored in the CAM. By using the structure and method the latency associated with tree search is significantly reduced.

    25.
    发明专利
    未知

    公开(公告)号：AT280411T

    公开(公告)日：2004-11-15

    申请号：AT00983409

    申请日：2000-12-21

    Applicant: IBM

    Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  DAVIS GORDON TAYLOR ,  GALLO ANTHONY MATTEO ,  HEDDES MARCO ,  JENKINS STEVEN KENNETH ,  LEAVENS ROSS BOYD ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

    IPC: H04L12/28 ,  H04L12/46 ,  H04L12/56 ,  H04L45/60 ,  G06F9/46 ,  H04L29/06

    Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.

    Method and system for reducing access to a memory
    26.
    发明专利
    Method and system for reducing access to a memory 未知

    公开(公告)号：CZ20032126A3

    公开(公告)日：2004-01-14

    申请号：CZ20032126

    申请日：2002-02-20

    Applicant: IBM

    Inventor： VERPLANKEN FABRICE JEAN ,  CALVIGNAC JEAN LOUIS ,  HEDDES MARCO ,  LOGAN JOSEPH FRANKLIN

    IPC: H04L12/861 ,  H04L12/00

    Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.

    Method and system for frame and protocol classification
    27.
    发明专利
    Method and system for frame and protocol classification 未知

    公开(公告)号：AU2016601A

    公开(公告)日：2001-07-16

    申请号：AU2016601

    申请日：2000-12-21

    Applicant: IBM

    Inventor： CALVIGNAC JEAN LOUIS ,  DAVIS GORDON TAYLOR ,  GALLO ANTHONY MATTEO ,  HEDDES MARCO ,  JENKINS STEVEN KENNETH ,  LEAVENS ROSS BOYD ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

    IPC: H04L12/28 ,  H04L12/46 ,  H04L12/56 ,  H04L45/60 ,  G06F9/46 ,  H04L29/06

    Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.

    28.
    发明专利
    未知

    公开(公告)号：DE69016018D1

    公开(公告)日：1995-02-23

    申请号：DE69016018

    申请日：1990-08-10

    Applicant: IBM

    Inventor： BEAULIEU CESCA JOSEPH ,  CALVIGNAC JEAN LOUIS ,  MILLET JEAN-MARC ,  NAUDIN BERNARD

    IPC: G06F13/00 ,  H04L1/16 ,  H04L1/18 ,  H04L29/06 ,  H04L29/08

    Abstract: The mechanism of the subject invention provides for an efficient interface between the hardware parts and software parts of communication modules used in a communication node wherein one module communicates with another module through a very high speed communication media. It insures the integrity of the data messages transferred between modules without impairing the performance of the data transfers. To deal with the problem of data message integrity at a very high speed, data link control DLC protocol relevant to steady state functions is implemented in hardware by finite state machines in the data store interfaces 14 and software running in microprocessor 16 is in charge of the initialization and recovery procedures.The steady functions are implemented by the hardware using sets of indicators in a request table which are representative of the transfer conditions, control blocks SCB which are representative of the transmission protocol variables and a message parameter/status field to carry the xmission protocol variables relevant to the message to the destination node. If an error is detected by the hardware part the indicators allows to freeze the operations of the hardware in order the microprocessor performs the error recovery functions using the transmission protocol variables in the control blocks.

    30.
    发明专利
    未知

    公开(公告)号：DE60132437T2

    公开(公告)日：2009-01-08

    申请号：DE60132437

    申请日：2001-03-26

    Applicant: IBM

    Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  HEDDES MARCO ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

    IPC: H04L12/54 ,  H04L47/52 ,  H04L47/56 ,  H04Q11/04

    Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

Patent Agency Ranking