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公开(公告)号：DE3684788D1
公开(公告)日：1992-05-21
申请号：DE3684788
申请日：1986-01-02
Applicant: IBM
Inventor： ARLINGTON DAVID L , CHEN CHIN-LONG , EVANS EDWARD K
Abstract: An extended error correction code operation particularly applicable to a code that can correct any number of errors in one sub-field or package but can only detect the existence of any number of errors in two sub-fields of a code word. If the initial pass of the data through the error correction code (ECC) logic (12) indicates an uncorrected error, the data is complemented and restored in the memory (10) and then reread. The retrieved data is recomplemented and again passed through the ECC logic (12). If an uncorrected error persists, then a bit-by-bit comparison (34) is performed between the originally read data (32) and the retrieved complemented data (30) to isolate the hard fails in the memory. The bits in the sub-field associated with the hard fail are then sequentially changed (20, 36, 38) and then the changed data word is passed through the ECC logic. A wrong combination is detected by the error correction code. The sequential changing continues until the bits in the sub-field associated with the hard fail match the originally stored data, in which case the error correction code logic can correct the remaining errors in the remaining sub-fields.
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公开(公告)号：AU4939390A
公开(公告)日：1990-09-13
申请号：AU4939390
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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Patent Agency Ranking
公开(公告)号：SG46485A1
公开(公告)日：1998-02-20
申请号：SG1996005030
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69029539T2
公开(公告)日：1997-07-17
申请号：DE69029539
申请日：1990-05-10
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , HSIAO MY-YUE
Abstract: An error correction coding system employs a single check symbol from an arbitrary sequence of information symbols to provide single error correction at the symbol level. The sequence of information symbols may in fact also be arbitrarily long. The coding system of the present invention provides both a method and apparatus for encoding the check symbol and a method and apparatus for error correction based upon the single coded symbol character. The system is particularly applicable for use in conjunction with bar code recognition systems but is in fact applicable to a broad range of coding systems, including optical character recognition and ordinary alphanumeric codes.
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公开(公告)号：DE69029539D1
公开(公告)日：1997-02-13
申请号：DE69029539
申请日：1990-05-10
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , HSIAO MY-YUE
Abstract: An error correction coding system employs a single check symbol from an arbitrary sequence of information symbols to provide single error correction at the symbol level. The sequence of information symbols may in fact also be arbitrarily long. The coding system of the present invention provides both a method and apparatus for encoding the check symbol and a method and apparatus for error correction based upon the single coded symbol character. The system is particularly applicable for use in conjunction with bar code recognition systems but is in fact applicable to a broad range of coding systems, including optical character recognition and ordinary alphanumeric codes.
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公开(公告)号：NZ232466A
公开(公告)日：1992-08-26
申请号：NZ23246690
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU623490B2
公开(公告)日：1992-05-14
申请号：AU4939390
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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