公开(公告)号：EP1997145A4

公开(公告)日：2011-07-06

申请号：EP07757883

申请日：2007-03-05

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7842

公开(公告)号：EP2108192A4

公开(公告)日：2009-12-30

申请号：EP07855285

申请日：2007-12-20

Applicant: IBM

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

公开(公告)号：EP1856740A4

公开(公告)日：2009-02-25

申请号：EP06718261

申请日：2006-01-12

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L29/00

CPC classification number: H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7842

Abstract: A semiconductor device structure includes a gate structure disposed on a portion of substrate, source and drain regions disposed adjacent to the portion so as to form a channel region in the portion, and trench isolation regions located immediately adjacent to the source and drain regions. At least portions of the trench isolation regions include stress materials such that the materials generate shear stresses in the channel region.

公开(公告)号：EP1683187A4

公开(公告)日：2008-08-27

申请号：EP04810633

申请日：2004-11-09

Applicant: IBM

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

公开(公告)号：EP1692717A4

公开(公告)日：2008-04-09

申请号：EP03819249

申请日：2003-12-08

Applicant: IBM

Inventor： BUEHRER FREDERICK WILLIAM ,  CHIDAMBARRAO DURESETI ,  DORIS BRUCE B ,  HUANG HSIANG-JEN ,  YANG HAINING

IPC: H01L21/336 ,  H01L21/22 ,  H01L21/265 ,  H01L21/324 ,  H01L21/425 ,  H01L21/8238 ,  H01L27/01 ,  H01L29/10 ,  H01L29/167 ,  H01L29/76

CPC classification number: H01L29/7842 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer ) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations and/or profiles/gradients. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

Abstract translation: 施加在由半导体材料的结构或主体（例如衬底或层）限定的边界上的应力膜提供了在接近边界的半导体材料中从拉应力至压应力的变化，并且用于修改退火期间的硼扩散速率和 从而改变最终的硼浓度和/或分布/梯度。 在场效应晶体管的情况下，栅极结构可以形成为具有或不具有侧壁以相对于源极/漏极，延伸和/或晕圈注入来调节边界的位置。 可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。 可以通过相同的工艺步骤同时实现nFET和pFET的结电容的降低。

公开(公告)号：JP2007129235A

公开(公告)日：2007-05-24

申请号：JP2006299336

申请日：2006-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78684

Abstract: PROBLEM TO BE SOLVED: To provide a FinFET including a gate electrode formed so as to cover a channel region of a semiconductor fin, and to provide a method of manufacturing the same.
SOLUTION: This semiconductor fin has a crystallographic orientation and a piezoresistance coefficient intrinsic to an axial direction. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. For this purpose, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region which complement the piezoresistance coefficient intrinsic to the axial direction.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种FinFET，其包括形成为覆盖半导体鳍片的沟道区域的栅电极，并提供其制造方法。 解决方案：该半导体鳍具有晶体取向和轴向固有的压阻系数。 形成栅电极，该固有应力确定为影响并优选地优化沟道区内的载流子迁移率。 为此，固有应力优选地在栅极电极和半导体鳍片沟道区域内提供与轴向固有的压阻系数相互补充的感应轴向应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007129223A

公开(公告)日：2007-05-24

申请号：JP2006294911

申请日：2006-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  UTOMO HENRY K

IPC: H01L29/786 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/045 ,  H01L29/7843 ,  H01L29/7845

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure using a semiconductor substrate having a channel region, and to provide a manufacturing method thereof. SOLUTION: A gate electrode is arranged on the semiconductor substrate. A spacer is arranged adjacently to a sidewall of the gate electrode. This spacer is formed of a material having a modulus of about 10-50 GPa. The modulus provides enhanced stress within the channel region. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用具有沟道区域的半导体衬底的半导体结构，并提供其制造方法。 解决方案：栅电极设置在半导体衬底上。 间隔件被布置成与栅电极的侧壁相邻。 该间隔物由具有约10-50GPa的模量的材料形成。 该模量在通道区域内提供增强的应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004193596A

公开(公告)日：2004-07-08

申请号：JP2003396240

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  BAIE XAVIER ,  MANDELMAN JACK A ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a field-effect transistor whose charge carrier mobility increases by the stress of an electric current channel 22.
SOLUTION: The direction of the stress is that in which a current flows (vertical direction). For a PFET device, the stress is compressive stress, while the stress is tensile stress in an NFET device. The stress is produced by a compressive film 34 located in an area 32 under the channel. The compressive film pushes up the channel 22 which bends the channel. In the PFET device, the compressive film is arranged under the edge 31 of the channel (e.g., under a source or drain) which compresses the upper part 22A of the channel. In the NFET device, the compressive film is arranged under the center 40 of the channel (e.g., under the gate) which pulls the upper part 22A of the channel. Therefore, both the NFET device and the PFET device can be strengthened. A method for manufacturing these devices is included.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2007103854A3

公开(公告)日：2008-04-10

申请号：PCT/US2007063275

申请日：2007-03-05

Applicant: IBM ,  CHIDAMBARRAO DURESETI

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7842

Abstract: An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate (600), comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the first areas is not parallel or perpendicular to the second crystalline orientation of the second areas. The integrated circuit further comprises first type devices (620) on the first areas and second type devices (630) on the second areas, wherein the first type devices (620) are parallel or perpendicular to the second type devices (630), and the first type devices (620) comprise a first current flow (621) and a second current flow (622) orthogonal to each other, wherein the carrier mobilities of the first (621) and second (622) current flows are equal to each other. Specifically, the first type devices comprise p-type field effect transistors (PFETs) and the second type devices comprise n-type field effect transistors (NFETs).

Abstract translation: 本发明的实施例的集成电路包括混合取向衬底（600），其包括具有第一结晶取向的第一区域和具有第二结晶取向的第二区域。 第一区域的第一晶体取向不平行或垂直于第二区域的第二晶体取向。 集成电路还包括第一区域上的第一类型设备（620）和第二区域上的第二类型设备（630），其中第一类型设备（620）平行或垂直于第二类型设备（630），并且 第一类型装置（620）包括彼此正交的第一电流（621）和第二电流（622），其中第一（621）和第二（622）电流的载流子迁移率彼此相等。 具体地，第一类型器件包括p型场效应晶体管（PFET），第二类型器件包括n型场效应晶体管（NFET）。

公开(公告)号：WO2005027192A3

公开(公告)日：2006-12-21

申请号：PCT/US2004028163

申请日：2004-08-30

Applicant: IBM ,  DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

Inventor： DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

Abstract translation: 提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力 在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。 应力由第一半导体晶格失配的第二半导体层施加。 第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。