公开(公告)号：GB2494311B

公开(公告)日：2013-10-23

申请号：GB201219460

申请日：2011-03-22

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  COHEN GUY ,  MAJUMDAR AMLAN ,  SLEIGHT JEFFREY

IPC: H01L29/06 ,  B82Y10/00 ,  G11C11/412 ,  G11C11/54 ,  H01L27/092 ,  H01L27/11 ,  H01L27/12 ,  H01L29/775 ,  H03K19/20

公开(公告)号：GB2498253A

公开(公告)日：2013-07-10

申请号：GB201222356

申请日：2012-12-12

Applicant: IBM

Inventor： SLEIGHT JEFFREY W ,  COHEN GUY ,  MAJUMDAR AMLAN ,  BANGSARUNTIP SARUNYA

IPC: G11C11/56 ,  H01L27/115 ,  H01L29/66 ,  H01L29/778

Abstract: A floating gate memory transistor 102, memory cell, and method of fabricating a device. The transistor includes one or more gated wires 104 substantially cylindrical, the transistor includes a first gate dielectric layer 106 at least partially covering the gated wires. The transistor further includes a plurality of gate nanocrystals 108 discontinuously arranged upon the first gate dielectric layer, the floating gate transistor also includes a second gate dielectric layer 110 covering the gate nanocrystals and the first gate dielectric layer. The crystals may be non-insulating and may be polysilicon. The charge trapping crystals store electric charge in the absence of an electric field. The transistor may further comprise an insulator layer 122 below the semiconductor layer 112 in which the wires are formed, the insulator layer having a recessed region 124 below the gate wires. The recess region may be covered by the first dielectric layer 106. The semiconductor layer may further comprise a drain pad 116 and source pad 114 which are connected by the gated wire. Silicide layers 118, 120 may be placed on the drain and source pads respectively. A gate conductor layer 128 may be placed on the second dielectric 110 layer. A planarized dielectric layer 130 may be included and a sidewall spacer 132 may separate the planarized dielectric layer and the gate conductor. The diameter of the gated wire may be less than 20nm.

公开(公告)号：GB2494947A

公开(公告)日：2013-03-27

申请号：GB201208378

申请日：2011-03-31

Applicant: IBM

Inventor： SLEIGHT JEFFREY ,  BANGSARUNTIP SARUNYA ,  COHEN GUY

IPC: H01L29/04 ,  H01L29/06 ,  H01L29/786

Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.

公开(公告)号：GB2494311A

公开(公告)日：2013-03-06

申请号：GB201219460

申请日：2011-03-22

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  COHEN GUY ,  MAJUMDAR AMLAN ,  SLEIGHT JEFFREY

IPC: H01L29/06 ,  B82Y10/00 ,  G11C11/412 ,  G11C11/54 ,  H01L27/092 ,  H01L27/11 ,  H01L27/12 ,  H01L29/775 ,  H03K19/20

Abstract: An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire.

公开(公告)号：DE112018000917T5

公开(公告)日：2019-11-14

申请号：DE112018000917

申请日：2018-04-18

Applicant: IBM

Inventor： HORESH LIOR ,  HORESH RAYA ,  COHEN GUY ,  VAN KESSEL THEODORE ,  WISNIEFF ROBERT LUKE

IPC: G03B17/12

Abstract: Verfahren und Systeme zum Reinigen einer optischen Einheit beinhalten Messen eines Zustands der optischen Einheit. Dabei wird ermittelt, ob die optische Einheit auf Grundlage des gemessenen Zustands der optischen Einheit gereinigt werden muss. Die optische Einheit wird mit Ultraschallschwingungen gereinigt, wenn die optische Einheit gereinigt werden muss.

公开(公告)号：DE112012001742T5

公开(公告)日：2014-01-16

申请号：DE112012001742

申请日：2012-03-05

Applicant: IBM

Inventor： GRILL ALFRED ,  COHEN GUY ,  DIMITRAKOPOULOS CHRISTOS D

IPC: H01L29/15

Abstract: Halbleiterstrukturen, die parallele Graphennanobänder oder Kohlenstoff-Nanoröhren aufweisen, die entlang kristallographischer Richtungen ausgerichtet sind, werden aus einer Vorlage aus Siliciumcarbid(SiC)-Finnen oder -Nanodrähten bereitgestellt. Die SiC-Finnen oder -Nanodrähte werden zuerst bereitgestellt, und anschließend werden durch Tempern Graphennanobänder oder Kohlenstoff-Nanoröhren auf den freigelegten Flächen der Finnen oder der Nanodrähte ausgebildet. Bei Ausführungsformen, bei denen geschlossene Kohlenstoff-Nanoröhren ausgebildet werden, werden die Nanodrähte vor dem Tempern frei hängen gelassen. Der Ort, die Ausrichtung und die Chiralität der Graphennanobänder und der Kohlenstoff-Nanoröhren, die bereitgestellt werden, werden durch die entsprechenden Siliciumcarbidfinnen und -Nanodrähte bestimmt, aus denen sie ausgebildet werden.

公开(公告)号：GB2497258A

公开(公告)日：2013-06-05

申请号：GB201306372

申请日：2011-08-29

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  COHEN GUY ,  NARASIMHA SHREESH ,  SLEIGHT JEFFREY

IPC: H01L29/775 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer.

公开(公告)号：GB2491778A

公开(公告)日：2012-12-12

申请号：GB201217774

申请日：2011-03-23

Applicant: IBM

Inventor： COHEN GUY ,  MURRAY CONAL E ,  ROOKS MICHAEL J

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

公开(公告)号：CA2843406A1

公开(公告)日：2012-10-26

申请号：CA2843406

申请日：2012-03-05

Applicant: IBM

Inventor： COHEN GUY ,  DIMITRAKOPOULOS CHRISTOS D ,  GRILL ALFRED

IPC: H01L29/15

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

公开(公告)号：GB2487316A

公开(公告)日：2012-07-18

申请号：GB201203673

申请日：2010-09-21

Applicant: IBM

Inventor： COHEN GUY ,  FRANK DAVID JAMES

IPC: B81B3/00

Abstract: A nonvolatile nano-electromechanical system device is provided and includes a cantilever structure, including a beam having an initial shape, which is supported at one end thereof by a supporting base and a beam deflector, including a phase change material (PCM), disposed on a portion of the beam in a non-slip condition with a material of the beam, the PCM taking one of an amorphous phase or a crystalline phase and deflecting the beam from the initial shape when taking the crystalline phase.