公开(公告)号：EP1854131A4

公开(公告)日：2011-03-30

申请号：EP06849665

申请日：2006-01-12

Applicant: IBM

Inventor： DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

IPC: H01L21/20 ,  B05C11/00 ,  B32B3/26

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

公开(公告)号：JP2000260999A

公开(公告)日：2000-09-22

申请号：JP2000050047

申请日：2000-02-25

Applicant: IBM

Inventor： CHONDROUDIS KONSTANTINOS ,  DIMITRAKOPOULOS CHRISTOS D ,  KAGAN CHERIE R ,  KYMISSIS IOANNIS ,  DAVID B MITSUI

IPC: H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L29/786 ,  H01L35/24 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: PROBLEM TO BE SOLVED: To provide an FET structure which uses an organic/inorganic by hybrid material as a semiconductor channel. SOLUTION: This FET structure uses an organic/inorganic hybrid material 32 as a semiconductor channel between a source electrode 34 and a drain electrode 36 in a device. The organic/inorganic material has advantages of an inorganic crystalline solid and an organic material. The inorganic element forms an extended inorganic one-dimensional, two-dimensional or three- dimensional network, and provides a high carrier mobility for an inorganic crystalline solid. The organic element promotes self assembly of these materials and permits adhesion of the materials under conditions of simple low- temperature treatment such as spin coating, dipping coating, thermal vapor- deposition, etc. In addition, the organic element is used to adjust the electronic characteristics of inorganic skeleton, by defining the dimension of the inorganic element and the electronic bonding between inorganic units.

公开(公告)号：JP2009044162A

公开(公告)日：2009-02-26

申请号：JP2008224431

申请日：2008-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GATES STEPHEN M ,  DIMITRAKOPOULOS CHRISTOS D ,  GRILL ALFRED ,  NGUYEN SON VAN

IPC: H01L21/312 ,  H01L21/768 ,  C23C16/00 ,  C23C16/40 ,  C23C16/56 ,  H01B3/46 ,  H01L21/31 ,  H01L21/316 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC classification number: H01L21/02126 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a dielectric material containing elements of Si, C, O and H, having specific mechanical property values (tensile stress, elastic modulus, hardness, cohesive force, and crack speed in water) which provide stable ultralow-k film without deterioration arising from steam or integration processing. SOLUTION: The dielectric materials 34, 38 and 44 have dielectric constants of approximately 2.8 or less, tensile stress of less than 45 Mpa, elastic modulus of somewhere between 2 and 15 GPa, hardness between around 0.2 to 2 GPa. Additionally, an electronic device structure containing the dielectric materials and various methods for producing them are disclosed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供含有Si，C，O和H元素的电介质材料，其具有特定的机械性能值（拉伸应力，弹性模量，硬度，内聚力和水中的裂纹速度），其提供稳定的 超低k电影没有蒸汽或整合处理的劣化。 电介质材料34,38和44具有约2.8或更小的介电常数，小于45Mpa的拉伸应力，2至15GPa之间的弹性模量，约0.2至2GPa之间的硬度。 另外，公开了包含电介质材料的电子器件结构及其制造方法。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：WO2007089223A3

公开(公告)日：2007-11-01

申请号：PCT/US2006001154

申请日：2006-01-12

Applicant: IBM ,  DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

Inventor： DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

IPC: H01L21/20 ,  B05C11/00 ,  B32B3/26

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Abstract translation: 描述了一种用于形成具有受控双轴应力的超低介电常数层的方法，其包括通过PECVD和旋涂涂覆之一形成含有Si，C，O和H的层并且在包含非常低浓度 的氧气和水每个小于10ppm。 还通过使用介电常数不超过2.8的方法来描述材料。 本发明克服了形成低双轴应力小于46MPa的薄膜的问题。

公开(公告)号：JP2005203794A

公开(公告)日：2005-07-28

申请号：JP2005007763

申请日：2005-01-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GATES STEPHEN M ,  DIMITRAKOPOULOS CHRISTOS D ,  GRILL ALFRED ,  NGUYEN SON VAN

IPC: H01L21/768 ,  C23C16/00 ,  C23C16/40 ,  C23C16/56 ,  H01L21/31 ,  H01L21/312 ,  H01L21/316 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC classification number: H01L21/02126 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a dielectric material which includes Si, C, O and H atoms and has specific mechanical characteristic (tensile stress, degree of elasticity, hardness, cohesive strength, crack velocity in water) values giving stable ultralow k film which is not deteriorated by steam or integration processing. SOLUTION: This dielectrics materials has an about ≤2.8 dielectric constant, tensile stress of less than 45 Mpas, degree of elasticity of about 2 to about 15 GPas, and hardness of about 0.2 to about 2 GPas. An electronic device structure including the dielectric materials by this invention and various methods by which the dielectrics materials of this invention are manufactured are also disclosed. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供包含Si，C，O和H原子的介电材料，具有特定的机械特性（拉伸应力，弹性，硬度，内聚强度，水中的裂纹速度），给出稳定的超低温 k膜不会因蒸汽或整合处理而恶化。 解决方案：该电介质材料具有约≤2.8介电常数，小于45Mpa的拉伸应力，约2至约15GPas的弹性度，以及约0.2至约2GPas的硬度。 还公开了包括本发明的电介质材料和制造本发明的电介质材料的各种方法的电子器件结构。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2000269515A

公开(公告)日：2000-09-29

申请号：JP2000064964

申请日：2000-03-09

Applicant: IBM

Inventor： ALESSANDRO SEZARE KAREGARI ,  DIMITRAKOPOULOS CHRISTOS D ,  PURUSHOTHAMAN SAMPATH

IPC: H01L51/05 ,  H01L21/00 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L29/786 ,  H01L51/30 ,  H01L51/40 ,  H01L51/00

Abstract: PROBLEM TO BE SOLVED: To widen a scope of material and process which can be used for a thin film transistor device by a method wherein, by use of an organic semiconductor layer coming into contact with a gate insulator of an inorganic mixture oxide, any one of the semiconductor layer and gate insulator is deposited to the other at substrate temperatures in a predetermined range. SOLUTION: An organic semiconductor layer 15 of a thin film transistor(TFT) device is deposited onto a gate insulation layer 13 as an inorganic oxide at temperatures close to room temperatures. An organic semiconductor material suitable therefor is pentacene. The TFT is constituted by depositing a source 16 and drain 17 to an exposed surface of the organic semiconductor layer 15 by a low temperatures deposition process at temperatures close to room temperatures in compliance with a position of a gate 12, so that a channel definition isolation region 18 is positioned at a center of the gate 12. The layer operating by deposition at the temperatures close to the room temperatures such as 25 deg.C to 150 deg.C is suitable for an appropriate dielectric property demanded for the organic semiconductor, and it becomes possible to process by a substrate enduring at fairly lower temperatures, and a use for such substrate is spread.

公开(公告)号：DE10006257A1

公开(公告)日：2000-09-14

申请号：DE10006257

申请日：2000-02-11

Applicant: IBM

Inventor： CHONDROUDIS KONSTANTINOS ,  DIMITRAKOPOULOS CHRISTOS D ,  KAGAN CHERIE R ,  KYMISSIS IOANNIS

IPC: H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L29/786 ,  H01L35/24 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L51/20

Abstract: Field effect transistor has a channel layer between source (34) and drain (36) regions, a gate region (40) arranged next to the channel layer, and an electrically insulating layer (38) between the gate region and the source region, the drain region and the channel layer. The channel layer (32) contains a semiconducting inorganic-organic hybrid material.

公开(公告)号：DE112012001742T5

公开(公告)日：2014-01-16

申请号：DE112012001742

申请日：2012-03-05

Applicant: IBM

Inventor： GRILL ALFRED ,  COHEN GUY ,  DIMITRAKOPOULOS CHRISTOS D

IPC: H01L29/15

Abstract: Halbleiterstrukturen, die parallele Graphennanobänder oder Kohlenstoff-Nanoröhren aufweisen, die entlang kristallographischer Richtungen ausgerichtet sind, werden aus einer Vorlage aus Siliciumcarbid(SiC)-Finnen oder -Nanodrähten bereitgestellt. Die SiC-Finnen oder -Nanodrähte werden zuerst bereitgestellt, und anschließend werden durch Tempern Graphennanobänder oder Kohlenstoff-Nanoröhren auf den freigelegten Flächen der Finnen oder der Nanodrähte ausgebildet. Bei Ausführungsformen, bei denen geschlossene Kohlenstoff-Nanoröhren ausgebildet werden, werden die Nanodrähte vor dem Tempern frei hängen gelassen. Der Ort, die Ausrichtung und die Chiralität der Graphennanobänder und der Kohlenstoff-Nanoröhren, die bereitgestellt werden, werden durch die entsprechenden Siliciumcarbidfinnen und -Nanodrähte bestimmt, aus denen sie ausgebildet werden.

公开(公告)号：CA2843406A1

公开(公告)日：2012-10-26

申请号：CA2843406

申请日：2012-03-05

Applicant: IBM

Inventor： COHEN GUY ,  DIMITRAKOPOULOS CHRISTOS D ,  GRILL ALFRED

IPC: H01L29/15

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

公开(公告)号：DE102012222116A1

公开(公告)日：2013-08-14

申请号：DE102012222116

申请日：2012-12-04

Applicant: IBM

Inventor： DIMITRAKOPOULOS CHRISTOS D ,  FARMER DAMON B ,  GRILL ALFRED ,  LIN YU-MING ,  NEUMAYER DEBORAH A ,  PFEIFFER DIRK ,  ZHU WENJUAN

IPC: H01L29/786 ,  H01L21/20 ,  H01L29/16

Abstract: Auf einer Oberseite einer Graphenschicht wird eine Siliciumnitridschicht bereitgestellt, und dann wird auf einer Oberseite der Siliciumnitridschicht eine Hafniumdioxidschicht bereitgestellt. Die Siliciumnitridschicht wirkt als ein Benetzungsmittel für die Hafniumdioxidschicht und verhindert dadurch die Bildung von diskontinuierlichen Hafniumdioxidsäulen über der Graphenschicht. Die Siliciumnitridschicht und die Hafniumdioxidschicht, die zusammen ein Doppelschicht-Gate-Dielektrikum mit geringer äquivalenter Oxiddicke (EOT) bilden, weisen über der Graphenschicht eine kontinuierliche Morphologie auf.