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    Asymmetric anti-halo field effect transistor
    21.
    发明专利
    Asymmetric anti-halo field effect transistor 未知

    公开(公告)号：GB2498621A

    公开(公告)日：2013-07-24

    申请号：GB201221477

    申请日：2012-11-29

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  NOWAK EDWARD ,  ANDERSON BRENT ALAN ,  ADKISSON JAMES WILLIAM

    IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423

    Abstract: In a method of forming an integrated circuit structure, a first compensating implant (Fig. 2; 120) with opposite dopant polarity to the semiconductor channel implant (Fig. 1; 114) is implanted uniformly into a substrate for example a silicon on insulator (SOI) substrate, to a depth shallower than a semiconductor channel implant depth. A mask 130 is patterned on the first compensating implant 122 in the substrate, including an opening 138 exposing a channel location of the substrate. A second compensating implant 140 called an anti-halo implant has doping polarity the same as the channel implant polarity, and is implanted into the channel location through the mask opening in the channel location and at an angle offset from perpendicular to the top surface of the substrate. The second compensating implant 142 is particularly useful for long channel transistors. It is positioned closer to a first side of the channel location relative to an opposite second side of the channel location. A gate insulator layer 132 and gate conductor (Fig. 5; 152) are formed above the channel location of the substrate in the mask opening 138. The mask is removed to leave the gate conductor standing on the channel location of the substrate. Source and drain extension regions (Fig. 6; 162) are formed by implanting using the gate structure as a mask, after which gate sidewalls (Fig. 7; 170) are formed and source and drain implants (Fig. 7; 174, 176) are implanted using the gate sidewalls as masks. The width of the anti-halo implant 142 is automatically matched to the width of gate.

    23.
    发明专利
    未知

    公开(公告)号：AT498199T

    公开(公告)日：2011-02-15

    申请号：AT03719421

    申请日：2003-03-19

    Applicant: IBM

    Inventor： CLARK WILLIAM ,  FRIED DAVID ,  LANZEROTTI LOUIS ,  NOWAK EDWARD

    IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786

    Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

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