公开(公告)号：GB2374984A

公开(公告)日：2002-10-30

申请号：GB0110072

申请日：2001-04-25

Applicant: IBM

Inventor： OGGIONI STEFANO ,  RAVANELLI ROBERTO

IPC: H01L23/498 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42

Abstract: A chip carrier (120), or an equivalent circuitised substrate, for high-frequency applications with a multi-layer structure, has via-holes (145) which extend between two non-adjacent conductive layers (210a,210f) for transmitting high-frequency signals. The chip carrier includes, for each via-hole, shielding rings (230b-230e) connectable to a reference voltage; each ring is formed in a corresponding intermediate conductive layer (210b-210e) between the two non-adjacent conductive layers, and is closed around the via-hole. The rings define a shielding coaxial structure for the via-hole. Preferably, the intermediate conductive layers are spaced apart from the via-hole, and particularly from respective lands (125,150), in order to reduce the capacitance of stray capacitors associated with the via-hole (without losing the shielding effect provided by the rings).

公开(公告)号：GB2344690A

公开(公告)日：2000-06-14

申请号：GB9826937

申请日：1998-12-09

Applicant: IBM

Inventor： BASSI LUIGI ,  OGGIONI STEFANO

IPC: H01L21/58 ,  H01L23/13

Abstract: A Plastic Ball Grid Array electronic package of the Cavity Down type particulary for use in high-frequency applications. In these packages the substrate has a cavity for receiving an active device (chip), which is usually attached to the substrate by means of the layer of glue. Due to the small dimensions of the chip and the gap between the chip and the cavity walls, it is extremely difficult to control the right quantity of glue in the dispensing operations. When the chip is pressed against the bottom of the cavity the glue may overflow and damage the circuits. According to the present invention, a secondary cavity is created inside the primary one and acts as a reservoir for the glue in excess.

公开(公告)号：IT201600072154A1

公开(公告)日：2018-01-11

申请号：IT201600072154

申请日：2016-07-11

Applicant: IBM

Inventor： OGGIONI STEFANO ,  DRAGONE SILVIO ,  HAGLEITNER CHRISTOPH

公开(公告)号：GB2520952A

公开(公告)日：2015-06-10

申请号：GB201321370

申请日：2013-12-04

Applicant: IBM

Inventor： BRUNSCHWILER THOMAS J ,  SCHLOTTIG GERD ,  OGGIONI STEFANO

IPC: H01L23/36 ,  H01L23/488

Abstract: An electronic device 200 of flip-chip type comprises at least one chip carrier 110 having a carrier surface 135, the carrier comprising one or more contact elements 140s,140p of electrically conductive material on the carrier surface, at least one integrated circuit chip 105 having a chip surface 120, the chip comprising one or more terminals 125s,125p of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material 150 soldering each terminal to the corresponding contact element, and restrain means 210s,210p around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements 205s,205p of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. The restrain means 210s,210p may have a surface phobic to solder material.

公开(公告)号：SG55406A1

公开(公告)日：1998-12-21

申请号：SG1997003942

申请日：1997-11-03

Applicant: IBM

Inventor： GARBELLI FRANCESCO ,  MONTI ALBERTO ,  OGGIONI STEFANO

IPC: H01L21/68 ,  H01L23/31 ,  H05K1/14 ,  H05K3/30

Abstract: In the manufacturing process of electronic modules a problem could arise when the modules have non-flat top surface. This is due to the fact that most of the automatic picking tools uses a vacuum nozzle to pick and place the module. According to the present invention a flat feature (a cap or a stud) is added to the module. This flat feature can be either fixed on the module or removable after the manufacture in order to reduce the dimensions.

公开(公告)号：GB2320132A

公开(公告)日：1998-06-10

申请号：GB9625233

申请日：1996-12-04

Applicant: IBM

Inventor： GARBELLI FRANCESCO ,  MONTI ALBERTO ,  OGGIONI STEFANO

IPC: H01L21/68 ,  H01L23/31 ,  H05K1/14 ,  H05K3/30 ,  H01L21/00 ,  H05K13/04

Abstract: In the manufacturing process of electronic modules a problem could arise when the modules have non-flat top surface. This is due to the fact that most of the automatic picking tools use a vacuum nozzle to pick and place the module. According to the present invention a flat feature 301 (e.g. a cap or a stud) is added to the module 101. This flat feature can be either fixed on the module or removable after the manufacture in order to reduce the dimensions.

公开(公告)号：GB2314463A

公开(公告)日：1997-12-24

申请号：GB9612769

申请日：1996-06-19

Applicant: IBM

Inventor： GARBELLI FRANCESCO ,  OGGIONI STEFANO

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34

Abstract: A Plastic Ball Grid Array electronic package having the conductive metal pads of variable area. The central pads are wider than those closer to the border for compensating the warpage effect on the final package.