公开(公告)号：GB2486378A8

公开(公告)日：2016-03-23

申请号：GB201205684

申请日：2010-09-08

Applicant: IBM

Inventor： ARSOVSKI IGOR ,  BRACERAS GEORGE ,  HOULE ROBERT M ,  PILO HAROLD

IPC: G11C7/04 ,  G11C7/08 ,  G11C7/14 ,  G11C7/22 ,  G11C11/413 ,  G11C11/419

Abstract: An SRAM delay circuit (14) that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal (13); a reference node (20) for capturing a reference current from a plurality of reference cells (12); a capacitance network (15) having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay (16), wherein the delay is controlled by the discharge of the capacitance network (15).

公开(公告)号：DE102012221806A1

公开(公告)日：2013-06-06

申请号：DE102012221806

申请日：2012-11-28

Applicant: IBM

Inventor： BRACERAS GEORGE M ,  PETERSON KIRK D ,  PILO HAROLD

IPC: G11C11/413

Abstract: Offenbart wird ein Speicherarray, bei dem für Bitzeilen-Voraufladevorgänge dynamisch die niedrigere von zwei Versorgungsspannungen von zwei Stromversorgungen ausgewählt wird. Im Speicherarray vergleicht ein Spannungsvergleicher die erste Versorgungsspannung auf einer ersten Stromversorgungsschiene mit einer zweiten Versorgungsspannung auf einer zweiten Stromversorgungsschiene und gibt ein Spannungsdifferenzsignal aus. Wenn das Spannungsdifferenzsignal einen ersten Wert besitzt, der angibt, dass die erste Versorgungsspannung gleich oder kleiner als die zweite Versorgungsspannung ist, stellt eine Steuerschaltung sicher, dass die mit einer Speicherzelle verbundenen komplementären Bitzeilen auf die erste Versorgungsspannung voraufgeladen werden. Wenn das Spannungsdifferenzsignal einen zweiten Wert besitzt, der angibt, dass die erste Versorgungsspannung größer als die zweite Versorgungsspannung ist, stellt die Steuerschaltung sicher, dass die komplementären Bitzeilen auf die zweite Versorgungsspannung voraufgeladen werden. Ebenfalls offenbart wird ein zugehöriges Verfahren.

公开(公告)号：AT407429T

公开(公告)日：2008-09-15

申请号：AT02787139

申请日：2002-07-11

Applicant: IBM

Inventor： NELSON ERIK A ,  PILO HAROLD

IPC: G11C11/413 ,  G11C29/00 ,  G11C29/06 ,  G11C29/28 ,  G11C29/34

Abstract: A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains th multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.

公开(公告)号：MY121171A

公开(公告)日：2005-12-30

申请号：MYPI20004629

申请日：2000-10-04

Applicant: IBM

Inventor： PILO HAROLD ,  COVINO JAMES J

IPC: G11C8/00 ,  G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: A COMPARATOR (40) AND VARIABLE DELAY (66,68) CIRCUIT ARE PROVIDED TO MAINTAIN THE TRACKING BETWEEN DATA AND ECHO CLOCKS IN A DOUBLE DATA RATE (DDR) RAM DEVICE (10). THIS IS ACCOMPLISHED BY PROVIDING A GLOBAL DATA SIGNAL (DUMMY DATA SIGNAL) THAT TRACKS WITH THE ACTUAL MEMORY ARRAY DATA. THIS GLOBAL DATA SIGNAL IS COMPARED TO THE TIMING OF THE RAM CLOCK (CLOCK) TO DETERMINE A DELAY TIME BETWEEN THE TWO BY WHICH THE PIPELINE CLOCKS (CLKRISE/CLKFALL) MUST BE DELAYED.AS A RESULT, THE PIPELINE CLOCKS ARE PUSHED OUT AS NEEDED SO THAT THEY ALWAYS TRANSITION AFTER THE ARRAY DATA ARRIVES AT THE OUTPUT LATCH.THEREFORE,AS CYCLE TIME DECREASES, BOTH ECHO CLOCKS AND DATA ARE PUSHED OUT IDENTICALLY AND MAINTAIN THEIR REQUIRED TRACKING.FIGURE 3

公开(公告)号：GB2358265B

公开(公告)日：2003-12-24

申请号：GB0024476

申请日：2000-10-06

Applicant: IBM

Inventor： PILO HAROLD ,  COVINO JAMES J

IPC: G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: A comparator and variable delay circuit are provided to maintain the tracking between data and echo clocks in a double data rate (DDR)RAM device. This is accomplished by providing a global data signal (dummy data signal) that tracks with the actual memory array data. This global data signal is compared to the timing of the RAM clock (CLOCK) to determine a delay time between the two by which the pipeline clocks (CLKRISE/CLKFALL) must be delayed. As a result, the pipeline clocks are pushed out as needed so that they always transition after the array data arrives at the output latch. Therefore, as cycle time decreases, both echo clocks and data are pushed out identically and maintain their required tracking.

公开(公告)号：GB2358265A

公开(公告)日：2001-07-18

申请号：GB0024476

申请日：2000-10-06

Applicant: IBM

Inventor： PILO HAROLD ,  COVINO JAMES J

IPC: G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: A comparator and variable delay circuit are provided to maintain the tracking between data and echo clocks in a double data rate (DDR)RAM device. This is accomplished by providing a global data signal (dummy data signal) that tracks with the actual memory array data. This global data signal is compared to the timing of the RAM clock (CLOCK) to determine a delay time between the two by which the pipeline clocks (CLKRISE/CLKFALL) must be delayed. As a result, the pipeline clocks are pushed out as needed so that they always transition after the array data arrives at the output latch. Therefore, as cycle time decreases, both echo clocks and data are pushed out identically and maintain their required tracking.