公开(公告)号：AU2003291666A1

公开(公告)日：2005-06-17

申请号：AU2003291666

申请日：2003-10-31

Applicant: IBM

Inventor： RECKTENWALD MARTIN ,  SANDON PETER A ,  HILGENDORF ROLF ,  LICHTENAU CEDRIC ,  PFLUEGER THOMAS

IPC: G06F1/08 ,  H03L7/16 ,  G06F17/50 ,  G06F1/04

公开(公告)号：AU2019376835A1

公开(公告)日：2021-04-22

申请号：AU2019376835

申请日：2019-11-05

Applicant: IBM

Inventor： GIAMEI BRUCE CONRAD ,  RECKTENWALD MARTIN ,  SCHMIDT DONALD WILLIAM ,  SLEGEL TIMOTHY ,  PURANIK ADITYA NITIN ,  FARRELL MARK ,  JACOBI CHRISTIAN ,  BRADBURY JONATHAN ,  ZOELLIN CHRISTIAN GERHARD

IPC: G06F9/30 ,  G06F9/38

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

公开(公告)号：GB2516477A

公开(公告)日：2015-01-28

申请号：GB201313191

申请日：2013-07-24

Applicant: IBM

Inventor： HABERMANN CHRISTIAN ,  RECKTENWALD MARTIN ,  KOCH GERRIT ,  TAST HANS-WERNER ,  JACOBI CHRISTIAN

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0897 ,  G06F12/1045 ,  G06F12/123

Abstract: A multi-level cache hierarchy structure with a first level, Ll, cache, being connected to a second level, L2, cache split into a L2 data cache directory and a L2 instruction cache. The L2 data cache directory comprises directory entries comprising information of data currently stored in the L1 cache. The first level cache is virtually indexed while the second and third levels are physically indexed, and allocating counter bits in a directory entry of tie L2 data cache directory for storing a counter number. The directory entry corresponds to at least one first Ll cache line; performing a first search in the Ll cache for a requested virtual memory address, wherein the virtual memory address corresponds to a physical memory address tag at a second L1 cache line. The directory entry may include least recently used bits to indicate cache lines for data replacement. The directory may be updated with a synonym index.

公开(公告)号：GB2507759A

公开(公告)日：2014-05-14

申请号：GB201220121

申请日：2012-11-08

Applicant: IBM

Inventor： TAST HANS-WERNER ,  RECKTENWALD MARTIN ,  HABERMANN CHRISTIAN ,  JACOBI CHRISTIAN

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0897

Abstract: A hierarchical cache 1 for a data processing system comprises a third level L3 cache 300, a second level L2 cache 200 and a first level L1 cache100. The first level cache is divided into a level one instruction L1i cache 10 and a level one data L1d cache 20. Similarly, the second level cache is divided into a level two instruction (L2i) cache 30 and a level two data (L2d) cache 40. The level three cache is a unified cache. The L1i cache can request data from the L2i cache, which can request data from the L3 cache. The L1d cache can request data from the L2i cache and the L3 cache. The L1 caches are indexed with virtual addresses, whereas the L2 and L3 caches are indexed with physical addresses. The L2 caches translate real addresses to virtual addresses.

公开(公告)号：GB2503437A

公开(公告)日：2014-01-01

申请号：GB201211273

申请日：2012-06-26

Applicant: IBM

Inventor： RECKTENWALD MARTIN ,  JACOBI CHRISTIAN ,  SLEGEL TIMOTHY J ,  ALEXANDER KHARY J

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0862

Abstract: A multiprocessor 100 may have a plurality of chips 32 each may have a plurality of cores 11 each comprising inclusive L1, L2 caches (20, 22). Each chip may also have a shared L3 cache 24 and the system may include an L4 cache 26 and memory 34. The system provides for fetching a cache line into a plurality of caches (20 ... 26) of the multilevel inclusive cache arrangement. A fetch request is sent from one cache to the next higher level cache; the request may be a prefetch request. The requested cache line is fetched in a first state, for example a read-only state, into one of the caches and fetched in a second state, such as an exclusive state, into at least one of the other caches.

公开(公告)号：GB2456677B

公开(公告)日：2012-02-15

申请号：GB0901180

申请日：2009-01-26

Applicant: IBM

Inventor： RECKTENWALD MARTIN ,  BILLECI MICHAEL

IPC: G06F11/22 ,  G06F11/36