公开(公告)号：JP2004363592A

公开(公告)日：2004-12-24

申请号：JP2004158994

申请日：2004-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHAHIDI GHAVAM G ,  BEDELL STEPHEN W ,  SADANA DEVENDRA K ,  FOGEL KEITH E

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a substantially relaxed high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion. SOLUTION: In order to form an injection rich area in a Si-containing substrate, ions are injected into Si-containing substrate at the beginning. The inplanted-ion rich region has sufficient ion concentration so that a barrier layer to disturb Ge diffusion is formed during annealing at a high temperature. Next, Ge-containing layer is formed on a surface of the Si-containing substrate, and then a heating process is performed at a temperature that enables the formation of a barrier layer, and the Ge interdiffusion. This allows a substantially relaxed single-crystal SiGe layer to be formed on the barrier layer. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004193596A

公开(公告)日：2004-07-08

申请号：JP2003396240

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  BAIE XAVIER ,  MANDELMAN JACK A ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a field-effect transistor whose charge carrier mobility increases by the stress of an electric current channel 22.
SOLUTION: The direction of the stress is that in which a current flows (vertical direction). For a PFET device, the stress is compressive stress, while the stress is tensile stress in an NFET device. The stress is produced by a compressive film 34 located in an area 32 under the channel. The compressive film pushes up the channel 22 which bends the channel. In the PFET device, the compressive film is arranged under the edge 31 of the channel (e.g., under a source or drain) which compresses the upper part 22A of the channel. In the NFET device, the compressive film is arranged under the center 40 of the channel (e.g., under the gate) which pulls the upper part 22A of the channel. Therefore, both the NFET device and the PFET device can be strengthened. A method for manufacturing these devices is included.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2011181955A

公开(公告)日：2011-09-15

申请号：JP2011111716

申请日：2011-05-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BENDERNAGEL ROBERT E ,  CHO KWANG SU ,  BIJAN DAVARI ,  FOGEL KEITH E ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G ,  TIWARY SANDIP

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/20

Abstract: PROBLEM TO BE SOLVED: To form a patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by a porous Si technique.
SOLUTION: A patterned SOI/SON composite structure and a method of forming the same are provided. In the SOI/SON composite structure, a patterned SOI/SON structure is sandwiched between an Si overlayer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes a shared processing treatment step wherein both SOI and SON structures are formed. This invention further provides a method of forming a composite structure including an embedded conductive/SON structure, and a method of forming a composite structure including only an embedded void plane.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：通过多孔Si技术形成图案化的绝缘体上硅（SOI）/无硅（SON）复合结构。 解决方案：提供了图案化的SOI / SON复合结构及其形成方法。 在SOI / SON复合结构中，图案化SOI / SON结构夹在Si覆层和半导体衬底之间。 形成图案化SOI / SON复合结构的方法包括形成SOI和SON结构的共同处理处理步骤。 本发明还提供一种形成包括嵌入式导电/ SON结构的复合结构的方法，以及形成仅包括嵌入的空隙平面的复合结构的方法。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2006032962A

公开(公告)日：2006-02-02

申请号：JP2005204182

申请日：2005-07-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G

IPC: H01L21/20

CPC classification number: H01L21/26506 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694

Abstract: PROBLEM TO BE SOLVED: To provide a method for suppressing the formation of flat surface defects, such as stacking faults and microtwins in a relaxed SiGe alloy layer.
SOLUTION: There is disclosed the method of manufacturing a substantially-relaxed SiGe alloy layer, in which flat surface defect density is decreased. The method comprises the steps of forming a strained Ge-containing layer on the front surface of an Si-containing substrate, implanting ions into the interface of the Ge-containing layer/the Si-containing substrate or under the interface, and forming the substantially-relaxed SiGe alloy layer, in which the flat surface defect density is decreased. Further, there are also provided a substantially relaxed SiGe-on-insulator, having an SiGe layer in which the flat surface defect density is decreased, and a heterostructure comprising the insulator.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种抑制在弛豫SiGe合金层中形成平坦表面缺陷的方法，例如层叠缺陷和微丝。 解决方案：公开了制造基本上松弛的SiGe合金层的方法，其中平坦表面缺陷密度降低。 该方法包括以下步骤：在含Si衬底的前表面上形成应变的含锗层，将离子注入含Ge层/含Si衬底的界面或界面之下，并形成基本上 不透明的SiGe合金层，其中平坦表面缺陷密度降低。 此外，还提供了具有其中平坦表面缺陷密度降低的SiGe层和包含绝缘体的异质结构的基本上松弛的绝缘体上SiGe。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005311367A

公开(公告)日：2005-11-04

申请号：JP2005119125

申请日：2005-04-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  DORIS BRUCE B ,  GUARINI KATHRYN W ,  LEONG MEIKEI ,  NARASIMHA SHREESH ,  REZNICEK ALEXANDER ,  KERN LIM ,  SADANA DEVENDRA K ,  SHI LEATHEN ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor device formed on a substrate having different crystal orientation.
SOLUTION: A method of forming a hybrid substrate containing strained Si and a strained Si containing hybrid substrate formed by this method are provided. In the present invention, a strained Si layer is formed on a semiconductor material, a second semiconductor layer, or both of them. According to the present invention, the strained Si layer has the same crystal orientation as either of a regrown semiconductor layer or the second semiconductor layer. This method provides the hybrid substrate wherein at least one of device layers contains the strained Si.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供形成在具有不同晶体取向的基板上的集成半导体器件。 解决方案：提供一种形成含有应变Si的混合基板和通过该方法形成的包含应变的含Si混合基板的方法。 在本发明中，在半导体材料，第二半导体层或它们两者上形成应变Si层。 根据本发明，应变Si层具有与重新生长的半导体层或第二半导体层中的任一个相同的晶体取向。 该方法提供混合基板，其中装置层中的至少一个包含应变Si。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005079602A

公开(公告)日：2005-03-24

申请号：JP2004256067

申请日：2004-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L21/66 ,  G01N21/84 ,  G01N21/95

CPC classification number: G01N21/9501 ,  G01N21/9505 ,  G01N2021/8461

Abstract: PROBLEM TO BE SOLVED: To provide a method for detecting crystal defect in a thin Si layer on a SiGe alloy layer.
SOLUTION: Defect etchant having high defect selectivity for Si 16 is used in this method. The defect etchant etches Si 16 to a thickness for a defect pit 18 to reach the SiGe layer 14 located under the Si 16. Next the second etchant that may be the same as the defect etchant or different from it is used to corrode the SiGe layer 14 under the pit while Si 16 is kept unhurt.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于检测SiGe合金层上的薄Si层中的晶体缺陷的方法。

解决方案：在该方法中使用对Si 16具有高缺陷选择性的缺陷蚀刻剂。 缺陷蚀刻剂将Si 16蚀刻到缺陷凹坑18的厚度以到达位于Si 16下面的SiGe层14.接下来，可以与缺陷蚀刻剂相同或不同于其的第二蚀刻剂腐蚀SiGe层 14在坑下，而Si 16保持不受伤害。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004214629A

公开(公告)日：2004-07-29

申请号：JP2003396383

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SADANA DEVENDRA K ,  BEDELL STEPHEN W ,  CHEN TZE-CHIANG ,  CHOE KWANG SU ,  FOGEL KEITH E

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L21/324 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02694 ,  H01L21/823807 ,  Y10S438/96

Abstract: PROBLEM TO BE SOLVED: To develop a new improved method for forming a relaxed SiGe-on-insulator substrate material which is thermodynamically stable with respect to the generation of a defect.
SOLUTION: Silicon to which tensile stress is applied is formed by epitaxially growing over the whole SiGe alloy layer. Silicon to which compressive stress is applied is formed by epitaxially growing over the whole porous silicon. A method of converting a patterned SOI region into patterned an SGOI (silicon-germanium ON oxide) by a SiGe/SOI heat mixing process for farther reinforcing the performance of a logic circuit in a padded DRAM is described in a preferred embodiment. The SGOI region in which Si is strained acts as a template for succeeding Si growth so that electrons and holes in the Si have higher mobilities.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2013181117A3

公开(公告)日：2014-04-03

申请号：PCT/US2013042772

申请日：2013-05-24

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  HEKMATSHOARTABARI BAHMAN ,  LAURO PAUL A ,  LI NING ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM G ,  SHAHRJERDI DAVOOD

IPC: H01L31/18

CPC classification number: H01L31/0684 ,  H01L21/02002 ,  H01L31/1896 ,  Y02E10/547

Abstract: A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.

Abstract translation: 以受控剥落方式使用的应力层通过使用可以断裂或溶解的裂开层去除。 在主体半导体衬底和金属应力层之间形成切割层。 受控的剥落过程将相对薄的残余主体衬底层与主体衬底分离。 在将手柄衬底附接到残留衬底层或随后在其上形成的其它层之后，解理层被溶解或以其他方式受到损害以便于去除应力层。 这种去除允许制造双面太阳能电池。

公开(公告)号：WO2007149581A3

公开(公告)日：2008-08-28

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 一种含半导体的异质结构，包括从底部到顶部的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，载流子在特定栅极偏置范围内被限制在沟道层上。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：WO2006017640B1

公开(公告)日：2006-04-27

申请号：PCT/US2005027691

申请日：2005-08-04

Applicant: IBM ,  BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/36 ,  H01L21/20 ,  H01L31/117

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

Abstract: A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer (41) of Si or Ge is deposited on a substrate (10) in a first depositing step; a second layer (42) of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer (50) having a plurality of Si layers and a plurality of Ge layers (41-44). The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer. The combined SiGe layer (50) is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer (61) on the combined SiGe layer (50); the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer (61) is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.

Abstract translation: 公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。 在第一沉积步骤中，在衬底（10）上沉积Si或Ge的第一层（41） 在第二沉积步骤中将另一元素的第二层（42）沉积在第一层上; 并重复第一沉积步骤和第二沉积步骤以形成具有多个Si层和多个Ge层（41-44）的组合SiGe层（50）。 Si层和Ge层的各自厚度符合组合SiGe层的所需组成比。 组合的SiGe层（50）的特征在于Si和Ge的数字合金，其导热率大于Si和Ge的无规合金的导热率。 该方法可以进一步包括在组合的SiGe层（50）上沉积Si层（61）的步骤; 组合的SiGe层的特征在于弛豫SiGe层，并且Si层（61）是应变Si层。 为了在SiGe层中具有更大的导热性，可以沉积第一层和第二层，使得每个层基本上由单一的同位素组成。