公开(公告)号：JP2003295792A

公开(公告)日：2003-10-15

申请号：JP2002150386

申请日：2002-05-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： TSUJIMURA TAKATOSHI ,  TANAKA ATSUSHI ,  MIWA KOICHI ,  MOROOKA MITSUO

IPC: H05B33/10 ,  G09F9/30 ,  G09G3/14 ,  H01L21/336 ,  H01L27/15 ,  H01L27/32 ,  H01L29/786 ,  H01L51/50 ,  H05B33/12 ,  H05B33/14 ,  H05B33/22

CPC classification number: H01L27/3244

Abstract: PROBLEM TO BE SOLVED: To provide an organic LED device which can cope with a large area, and to provide its efficient manufacturing method. SOLUTION: This organic LED device 10 is constituted on an insulation substrate 26 and includes switching TFT 12 and a driver TFT 14 formed on the substrate 26. Further, an organic LED element 16 is formed for every pixel through an insulation film 58 on the substrate 26, and connected to the driver TFT. This organic LED device 10 comprises an anode 34 and a cathode 36 connecting the driver TFT 12 and the organic LED element 16 formed on the upper side of the insulation film 58, the anode 34 connects a plurality of pixels as a common electrode and self-aligning property at the time of manufacturing is improved. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种能够应对大面积的有机LED装置，并提供其有效的制造方法。 解决方案：该有机LED器件10构成在绝缘基板26上，并且包括形成在基板26上的开关TFT 12和驱动TFT 14.此外，通过绝缘膜58形成每个像素的有机LED元件16 并且连接到驱动器TFT。 该有机LED器件10包括连接驱动TFT12和形成在绝缘膜58的上侧的有机LED元件16的阳极34和阴极36，阳极34连接作为公共电极的多个像素， 提高了制造时的对准性。 版权所有（C）2004，JPO

公开(公告)号：JP2002076366A

公开(公告)日：2002-03-15

申请号：JP2001170713

申请日：2001-06-06

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  PETER FRYER ,  ROBERT L WISUNIFU

IPC: G02F1/1335 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To greatly improve the process required for manufacturing and reduce a leakage current between electrodes by forming offset regions in a multilayer film structure such as thin film transistors. SOLUTION: The multilayer film structure comprises source electrodes 14 and drain electrodes 15 formed by plating with specified spacings above an insulation substrate 11, an amorphous silicon film 16 facing the source electrodes 14 and the drain electrodes 15, a gate insulation film 17 laid on this film 16, and gate electrodes 18 laid by plating on the gate insulation film 17. The amorphous silicon film 16 and the gate insulation film 17 have offset regions 20 around the gate electrodes 18, but these regions 20 locate neither above nor below the gate electrodes 18.

公开(公告)号：JP2001196591A

公开(公告)日：2001-07-19

申请号：JP2000004301

申请日：2000-01-13

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  TOKUHIRO OSAMU ,  MOROOKA MITSUO ,  MIYAMOTO TAKASHI

IPC: G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To reduce leakage current at a floating island formed on a thin-film transistor. SOLUTION: A source electrode 14 and a drain electrode 15, provided above an insulating substrate 11 at a prescribed interval, an a-Si film 16 provided to them, a gate insulating film 17 stacked on the a-Si film 16, and a gate electrode 18 stacked on the gate insulating film 17, are provided. The a-Si film 16 comprises a floating inland 20, which is not present above and below the gate electrode 18, while being present between the source electrode 14 and the drain electrode 15. The boron ion is implanted in the region, to form a boron ion implantation region 19.

公开(公告)号：JP2001196589A

公开(公告)日：2001-07-19

申请号：JP2000000022

申请日：2000-01-04

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  MIYAMOTO TAKASHI

IPC: H01L21/336 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a TFT structure through a two-mask process. SOLUTION: A light blocking layer and an interlayer insulating layer are successively laminated on a substrate, a source electrode and a drain electrode are formed thereon (first mask process), a semiconductor layer, a gate insulating layer, and a gate metal layer are laminated successively covering the electrodes, a gate electrode is formed in a second mask process, then the gate insulating layer and the semiconductor layer are etched, and the interlayer insulating film and the light blocking layer are etched using the source and drain electrode as a mask, to obtain a top gate TFT structure. At this point, when each of the interlayer insulating layer and the gate insulating layer is formed of insulating materials, whose main components are SiOX and SiNX respectively and a plasma etching operation is carried out by the use of a mixed gas of CF4 and hydrogen, the gate insulating layer and the semiconductor layer are overetched naturally as against the interlayer insulating layer and the light block layer, so that a TFT structure of high reliability and free of troubles, such as an optical leakage current, can be obtained.

公开(公告)号：JP2001077366A

公开(公告)日：2001-03-23

申请号：JP23392099

申请日：1999-08-20

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  TOKUHIRO OSAMU ,  MIYAMOTO TAKASHI ,  MOROOKA MITSUO

IPC: H01L21/205 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/786 ,  G02F1/1365

Abstract: PROBLEM TO BE SOLVED: To improve productivity in the deposition of the a-Si film of a thin film transistor and also enhance the thin film transistor in characteristics. SOLUTION: An amorphous silicon film 2, a gate insulating film 3, a gate insulating film 3, and a gate electrode 4 are sequentially laminated on an insulating substrate 1 for the formation of a thin film transistor. In this case, the amorphous silicon film 2 is composed of a low-defect density amorphous silicon layer 5 that is formed at a low deposition rate and a high-speed amorphous silicon layer 6 formed at a higher deposition rate than the silicon layer 5, where the amorphous silicon layer 5 is located closer to the insulating board 1 than the amorphous silicon layer 6, and the amorphous silicon layer 6 is formed coming into contact with the under surface of the gate insulating film 3.

公开(公告)号：JP2003302936A

公开(公告)日：2003-10-24

申请号：JP2002097545

申请日：2002-03-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： TSUJIMURA TAKATOSHI ,  MIWA KOICHI ,  MOROOKA MITSUO

IPC: H01L51/50 ,  G09G3/20 ,  G09G3/30 ,  G09G3/32 ,  H05B33/14

CPC classification number: G09G3/3233 ,  G09G2300/0417 ,  G09G2300/0842 ,  G09G2310/0254 ,  G09G2310/066 ,  G09G2320/0233 ,  G09G2320/043

Abstract: PROBLEM TO BE SOLVED: To reduce a plus shift of threshold voltage (Vth) generated in a thin film transistor when driving OLED by the thin film transistor. SOLUTION: An increase component of the threshold voltage (Vth) is removed by simultaneously switching on-off the gate voltage and drain voltage by an amorphous silicon TFT as a transistor for driving the OLED (Organic Light Emitting Diode). Namely, the OLED display 10 is provided with a driving circuit 20 for driving the OLED by the amorphous silicon TFT, and a supply line driver 14 for switching off the voltage to be supplied to the drain electrode in the amorphous silicon TFT when switching on-off the gate voltage to the gate electrode in the amorphous silicon TFT of the driving circuit 20. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：为了减少在通过薄膜晶体管驱动OLED时在薄膜晶体管中产生的阈值电压（Vth）的正移相。 解决方案：通过非晶硅TFT作为用于驱动OLED（有机发光二极管）的晶体管同时接通栅极电压和漏极电压来消除阈值电压（Vth）的增加分量。 也就是说，OLED显示器10设置有用于通过非晶硅TFT驱动OLED的驱动电路20，以及用于在切换开关时切断供给非晶硅TFT中的漏电极的电压的电源线驱动器14。 关闭驱动电路20的非晶硅TFT中的栅电极的栅极电压。（C）2004，JPO

公开(公告)号：JP2003218498A

公开(公告)日：2003-07-31

申请号：JP2002290197

申请日：2002-10-02

Applicant: IBM

Inventor： PAUL S ANDREE ,  JOHN C FLAKE ,  MICHEL BRUNO ,  TSUJIMURA TAKATOSHI

IPC: G02F1/1343 ,  G09F9/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/288 ,  H01L21/768 ,  H01L51/50 ,  H05K3/18 ,  H05K3/38 ,  H05B33/14

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming pattern, a semiconductor device and a metal conductive pattern. SOLUTION: A method of forming pattern includes the steps of: preparing a substrate; (202) forming an insulating layer having OH functional groups on a surface of the insulating layer; (203) forming a patterned polymer layer on the insulating layer; patterning the polymer layer by etching the insulating layer; exposing the insulating layer by peeling off (205) the polymer layer; and (207) selectively depositing conductive materials on the insulating layer. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002244586A

公开(公告)日：2002-08-30

申请号：JP2001029587

申请日：2001-02-06

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  MAKITA ATSUYA ,  ARAI TOSHIAKI

IPC: G02F1/1333 ,  G02F1/1345 ,  G09F9/00 ,  G09F9/30 ,  H01L21/3205 ,  H01L23/52 ,  H01L27/12 ,  H01L51/50 ,  H05B33/14 ,  H05B33/26

Abstract: PROBLEM TO BE SOLVED: To provide an array substrate for display, the manufacturing method of the array substrate for display and a display device in which the array substrate for display is used. SOLUTION: This substrate is an array substrate for display in which a thin film transistor array which is formed on an insulating substrate 1, plural wirings 23, 24 which are arranged on the insulating substrate 1, connection pads 25, 27 which are arranged at one ends of the wirings 23, 24 and are connected respectively to these wirings 23, 24 and pixel electrodes 22 are included and, moreover, in the substrate, dummy conductive patterns 29 are arranged among end parts of the connection pads 25, 27 and end parts of the pixel electrodes 22.

公开(公告)号：JP2002043575A

公开(公告)日：2002-02-08

申请号：JP2000208593

申请日：2000-07-10

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  TOKUHIRO OSAMU ,  MIWA KOICHI ,  MOROOKA MITSUO

IPC: G02F1/1333 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To improve the reliability of an active matrix substrate by preventing the corrosion, etc., of lead-out wiring by covering the wiring with a gate insulating film or ITO without adding any patterning process and, in addition, improving the manufacturing yield of the substrate. SOLUTION: This active matrix substrate is provided with a source electrode 14 and a drain electrode 15 which are arranged above an insulating substrate 11 with a prescribed clearance in between; an a-Si film 17, a gate insulating film 18, and a gate electrode 19 successively laminated upon the electrodes 14 and 15; and an ITO 20 having a first portion which is laminated upon the gate electrode 19 and has the same patterned surface as the electrode 19 has and a second portion which is formed to partially cover the source electrode 14 and forms a picture element electrode. The substrate is also provided with a data line 16 which is connected to the drain electrode 15 and covered with another gate insulating film 18.

公开(公告)号：JP2001338880A

公开(公告)日：2001-12-07

申请号：JP2000156007

申请日：2000-05-26

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  TOKUHIRO OSAMU ,  MOROOKA MITSUO ,  MIYAMOTO TAKASHI

IPC: G02F1/136 ,  C23C16/44 ,  G02F1/1368 ,  G09F9/00 ,  H01L21/00 ,  H01L21/205 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method and device that can improve productivity, and can reduce costs for manufacturing an active matrix device including a top-gate-type TFT without poorly affecting the characteristics of the TFT. SOLUTION: This method includes a process that forms oxide coating 15 on the internal wall of a treatment chamber 9 for CVD in the manufacture of the top-gate-type TFT, a process that arranges a substrate 1 where source and drain electrodes 5 and 4 are formed in the treatment chamber 9, a process that carries out P doping to the source and drain electrodes 5 and 4, and a process that forms an a-Si layer 6 and a gate insulating film 7 in the treatment chamber. Also, this device manufactures the active matrix device including the top-gage-type TFT where the inner surface of the treatment chamber 9 is coated with the oxide coating 15.