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    INTERCONNECTION OF OPPOSITE CONDUCTIVITY TYPE SEMICONDUCTOR REGIONS
    21.
    发明专利
    INTERCONNECTION OF OPPOSITE CONDUCTIVITY TYPE SEMICONDUCTOR REGIONS 未知

    公开(公告)号：CA1142261A

    公开(公告)日：1983-03-01

    申请号：CA349766

    申请日：1980-04-14

    Applicant: IBM

    Inventor： NING TAK H ,  WIEDMANN SIEGFRIED K

    IPC: H01L21/8222 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/06 ,  H01L29/43 ,  H01L21/44

    Abstract: A technique for making ohmic electrical interconnections between semiconductor regions of opposite conductivity type, without requiring metallic interconnection lines. This technique has applicability in any circuit using bipolar devices, and in particular is useful to provide a very dense static memory array of bipolar transistors, To join the opposite conductivity regions, intermediate layers are formed including a silicide of a refractory metal, such as W, Mo, Ta, etc. and at least one layer of doped polycrystalline silicon having M and P type regions, the refractory metal silicide forms an electrical connection to at least one doped polysilicon layer of a first conductivity type and to either a single crystal semiconductor region of the opposite conductivity type or to another polysilicon layer which also has the opposite conductivity type. As an example, an N type silicon region is interconnected to a P type silicon region by intermediate layers of N pol licon - refractory metal silicide - P polysilicon.

    STABILITY TESTING OF SEMICONDUCTOR MEMORIES
    26.
    发明专利
    STABILITY TESTING OF SEMICONDUCTOR MEMORIES 未知

    公开(公告)号：CA1238124A

    公开(公告)日：1988-06-14

    申请号：CA499842

    申请日：1986-01-17

    Applicant: IBM

    Inventor： ANDRUSCH GEORG ,  BAISCH JOACHIM ,  BARSUHN HORST ,  WERNICKE FRIEDRICH C ,  WIEDMANN SIEGFRIED K

    IPC: G11C29/00 ,  G11C11/401 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56 ,  G01R31/26

    Abstract: STABILITY TESTING OF SEMICONDUCTOR MEMORIES Design/test technique to facilitate improved long-term stability testing of static memory arrays with high inherent data retention characteristics at extremely small standby current requirements. The test concept is based on the fact that defects in the standby condition system of a memory array have a bearing on the word line standby potential. Detection of word line potentials differing from their nominal value defined for the standby state, i.e. in the unselected operation mode, is accomplished by performing a disturb write operation into the partly or totally unselected array. As a result cells along a defect word line are less disturbed than those along a good one. This (inverted error pattern) is used for screening defect word lines which otherwise would show up as (long-term) data retention problems.

    SEMICONDUCTOR DEVICE HAVING PAIRS OF VERTICAL COMPLEMENTARY BIPOLAR TRANSISTORS AND METHOD OF FABRICATION THEREFOR
    27.
    发明专利
    SEMICONDUCTOR DEVICE HAVING PAIRS OF VERTICAL COMPLEMENTARY BIPOLAR TRANSISTORS AND METHOD OF FABRICATION THEREFOR 未知

    公开(公告)号：DE3066684D1

    公开(公告)日：1984-03-29

    申请号：DE3066684

    申请日：1980-06-24

    Applicant: IBM

    Inventor： SILVESTRI VICTOR J ,  TANG DENNY D ,  WIEDMANN SIEGFRIED K

    IPC: H01L27/082 ,  G11C11/411 ,  H01L21/331 ,  H01L21/74 ,  H01L21/763 ,  H01L21/8226 ,  H01L21/8228 ,  H01L27/02 ,  H01L29/73 ,  H01L21/82 ,  G11C11/40

    Abstract: A vertical pair of complementary, bipolar transistors is disclosed which includes a semiconductor substrate of one conductivity type and a pair of dielectric isolation regions disposed in contiguous relationship with the substrate. An injector region of opposite conductivity type is disposed between the pair of isolation regions. A pair of heavily doped, polycrystalline, semiconductor regions of the one conductivity type is disposed over and in registry with the pair of isolation regions. Similarly, a single crystal, semiconductor region of the one conductivity type is disposed over and in registry with the injector region. Finally, a first zone of opposite conductivity type is disposed in the single crystal region and a second zone of the one conductivity type is disposed in the first zone. In addition, a method of manufacturing a semiconductor device having vertical complementary, bipolar transistors is disclosed which includes the steps of forming regions of dielectric isolation which are contiguous with a semiconductor substrate and a region of semiconductor of one conductivity type therebetween, the semiconductor substrate being of opposite conductivity type; forming regions of heavily doped, polycrystalline semiconductor of the opposite conductivity type and a region of single crystal semiconductor of the opposite conductivity type in registry with the regions of dielectric isolation and the semiconductor region of one conductivity type, respectively. The method also includes the step of forming a zone of one conductivity type in the region of single crystal semiconductor and a zone of opposite conductivity type in the zone of one conductivity type.

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