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    INTEGRATED CIRCUIT AND ITS MANUFACTURE
    21.
    发明专利
    INTEGRATED CIRCUIT AND ITS MANUFACTURE 失效

    公开(公告)号：JP2000252364A

    公开(公告)日：2000-09-14

    申请号：JP2000047093

    申请日：2000-02-24

    Applicant: IBM ,  SIEMENS AG

    Inventor： BRINTZINGER AXEL ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  KAARU JIEI RADENSU

    IPC: H01L21/82 ,  G11C29/04 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/02 ,  H01L27/108 ,  G11C29/00

    Abstract: PROBLEM TO BE SOLVED: To provide a fuse link structure which reduces the magnitude of damage which is caused when a fuse element is blown and to provide its method. SOLUTION: This integrated circuit is provided with a main element 102. The integrated circuit is provided with a redundant element 104 which is replaced selectively with the main element 102 by at lease one fuse. The fuse contains a first layer 401 which comprises at least one fuse link region 402, contains a second layer 401 on the first layer, a gap 410 inside the second layer on the fuse link region 402, and contains a fuse window 408 in a dielectric layer 407. Since the gap 410 guides energy and a fuse material to the fuse window 408 from the fuse link region 402, it is possible to reduce damage to a circumferential structure.

    SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
    22.
    发明专利
    SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效

    公开(公告)号：JP2000091438A

    公开(公告)日：2000-03-31

    申请号：JP23860699

    申请日：1999-08-25

    Applicant: SIEMENS AG ,  IBM

    Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  DANIEL GABRIEL ,  EINSPRUCH FRED

    IPC: H01L21/82 ,  G11C29/04 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/00 ,  H01L27/108 ,  G11C29/00

    Abstract: PROBLEM TO BE SOLVED: To enable electrical fusion at the voltage of a specific value by connecting a fuse link at its one end with an individual connector terminal having a sectional region larger than its sectional region, and by connecting the fuse link at its other end with a common connector terminal having a sectional region which is larger than that of the sectional region of the individual connector terminal. SOLUTION: A semiconductor device 40 includes a board 41, on whose surface there is provided a redundant operating wiring, including many fuse-links 44 or a fuse bank used as a severe pitch array 42 for custom wirings. The fuse link 44 is connected at its one end with an individual connector terminal 43, having a sectional region about twice as large as its sectional region to be connected at its other end, with a common connector terminal 45 having a sectional region about twice as large as that of the individual connector terminal 43. As a result, heating caused by the maximized resistance difference between the fuse link 44 and the common connector terminal 45 is promoted to make possible electrical fusion at a voltage of about 10 V.

    Method of reducing stress within metallic cover of integrated circuit, and integrated circuit produced using the method
    23.
    发明专利
    Method of reducing stress within metallic cover of integrated circuit, and integrated circuit produced using the method 审中-公开
    集成电路金属外壳中应力减小的方法和使用该方法生产的集成电路

    公开(公告)号：JPH11274158A

    公开(公告)日：1999-10-08

    申请号：JP4899

    申请日：1999-01-04

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

    Inventor： ARNDT KENNETH C ,  CONTI RICHARD A ,  DOBUZINSKY DAVID M ,  ECONOMIKOS LAERTIS ,  GAMBINO JEFFREY P ,  HOH PETER D ,  NARAYAN CHANDRASEKHAR

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

    CPC classification number: H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    Abstract: PROBLEM TO BE SOLVED: To check cracks within a final passivation laver 13 of an integrated circuit by reducing the stresses within a peripheral dielectric which are due to acute corner of a circuit pattern.
    SOLUTION: Stresses generally induced inside a dielectric is reduced by formings 15 and 17, at lower corner 14" of a circuit pattern 11 before adhering an outer layer (that is, a passivation layer) 13. When patterning it by metallic RIE process, this kind of rounding of the corner is achieved by a two-step metallic etching process, including the first step of creating a vertical sidewall and the second step of tapering the lower part of the vertical sidewall or creating a tapered spacer 15 along the under section of the vertical sidewall. When patterning it by a die machine process, this kind of rounding of the corner is achieved by a two-step trench etching process, including a first step of creating a vertical sidewall and a second step of creating a tapered side wall along the under section of the vertical sidewall.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：通过减少外围电介质中由于电路图案的急剧拐角引起的应力来检查集成电路的最终钝化层13内的裂纹。 解决方案：在粘附外层（即钝化层）13之前的电路图案11的下角14“处，通过结构15和17减小电介质内部的应力。当通过金属RIE工艺对其进行图案化时， 通过两步金属蚀刻工艺实现角部的圆角化，包括形成垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤或者沿着垂直侧壁的下部形成锥形间隔件15 垂直侧壁，当通过模具机加工对其进行图案化时，通过两步沟槽蚀刻工艺实现角部圆化，包括形成垂直侧壁的第一步骤和产生锥形侧壁的第二步骤 沿着垂直侧壁的下部。

    INTEGRATED CIRCUIT
    24.
    发明专利
    INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11163146A

    公开(公告)日：1999-06-18

    申请号：JP27611398

    申请日：1998-09-29

    Applicant: SIEMENS AG ,  IBM

    Inventor： NARAYAN CHANDRASEKHAR ,  DINKEL BETTINA

    IPC: H01L21/82 ,  H01L23/31 ,  H01L23/525

    Abstract: PROBLEM TO BE SOLVED: To conform a small TV window to a precursory fuse designing specification, which covers only a small space. SOLUTION: After the formation of a sensing soft passivation film 150, an etching stopper film 130 is used so as to set up a terminal through the intermediary of an aperture 132 to access a device feature part. As a result of etching film, the size of the terminal set up through the intermediary of the aperture 132 through an etching film is decided by decoupling with the decomposition activity of the existing photosensing soft passivation film 150.

    INTEGRATED CIRCUIT AND DYNAMIC RANDOM ACCESS MEMORY INTEGRATED CIRCUIT
    25.
    发明专利
    INTEGRATED CIRCUIT AND DYNAMIC RANDOM ACCESS MEMORY INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11154739A

    公开(公告)日：1999-06-08

    申请号：JP25842598

    申请日：1998-09-11

    Applicant: SIEMENS AG ,  IBM

    Inventor： WEIGAND PETER ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH C ,  LACHTRUPP DAVID ,  GILMOUR RICHARD ALFRED ,  PALAGONIA ANTHONY MICHAEL

    IPC: H01L21/82 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To minimize damage to a substrate being subjected to fuse operation and to reduce the fuse pitch, by arranging a screening part where a laser fuse link is set by laser beams so that the damage of laser induction from laser beams is minimized at a region below the screening part. SOLUTION: A dynamic access memory integrated circuit has a plurality of screening parts 402, 404, 406, and 408 located on the lower side of laser fuse links 202, 204, 206, and 208. The screening parts are constituted so that a first regions located on the lower side of the screening parts can be essentially minimized when the first laser fuse links are set by laser beams. The screening part is formed by a material for reflecting nearly entire laser energy applied the screening part. A reflection material such as tungsten, molybdenum, platinum, chromium, titanium, and their alloys operates favorably.

    26.
    发明专利
    未知

    公开(公告)号：DE60307793T2

    公开(公告)日：2007-08-23

    申请号：DE60307793

    申请日：2003-02-27

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： IYER S SUNDAR K ,  IYER SUBRAMANIAN S ,  KOTHANDARAMAN CHANDRASEKHARAN ,  NARAYAN CHANDRASEKHAR

    IPC: H01L23/525

    Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link. In another embodiment, the temperature gradient is increased by selectively varying the thickness of the underlying oxide layer such that the cathode is disposed on a thinner layer of oxide than the fuse link.

    28.
    发明专利
    未知

    公开(公告)号：DE69633998T2

    公开(公告)日：2005-12-22

    申请号：DE69633998

    申请日：1996-09-04

    Applicant: IBM

    Inventor： CIPOLLA THOMAS M ,  COLGAN EVAN ,  MELCHER ROBERT L ,  MOK LAWRENCE S ,  NARAYAN CHANDRASEKHAR ,  SHI LEATHEN ,  YANG KEI-HSIUNG

    IPC: G02F1/13 ,  G02F1/133 ,  G02F1/1333 ,  G02F1/136 ,  G09F9/00 ,  H04N5/74 ,  G02F1/1335 ,  H04N9/31

    Abstract: A liquid crystal element, a packaging structure providing thermal and alignment control, a display device including the same, and methods of fabrication and assembly are provided. The liquid crystal element includes: a semiconductor wafer, having microcircuitry and an array of reflective pixels; a layer of electro-optical responsive liquid crystal medium, of uniform thickness, disposed on the reflective pixels; a transparent conductive layer positioned on the liquid crystal, being substantially parallel to the reflective layers, to ensure a uniform thickness of the liquid crystal; and an insulative transparent layer provided on the conductive layer. The liquid crystal element is laminated to an optically flat substrate to limit the out-of-plane distortions thereof. The structure formed by element and substrate are disposed in a substrate holder which is mounted to a wiring board, and coupled to voltage sources for actuating the liquid crystal. During mounting, an aligning fixture is used to ensure proper orientation of the element relative to the related optical elements. Once the element is positioned, a heat sink is coupled to the rear surface of the substrate holder to dissipate heat.

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