公开(公告)号：DE60305208D1

公开(公告)日：2006-06-14

申请号：DE60305208

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：DE102005055436A1

公开(公告)日：2006-06-01

申请号：DE102005055436

申请日：2005-11-21

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC CORBEI

Inventor： BRAUN DANIEL ,  GOGL DIETMAR

IPC: H01L27/22 ,  G11C11/15

Abstract: The chip has a set of magnetoresistive memory cells each including a magnetic tunnel junction having fixed and free magnetic regions. The free magnetic region includes two ferromagnetic layers that are antiferromagnetically coupled, where a coil surrounds the memory chip for creating a magnetic offset field. The regions are stacked in a parallel, overlying relationship separated by a layer of non-magnetic material. An independent claim is also included for a method of writing to a random access memory.

公开(公告)号：AU2003294886A8

公开(公告)日：2004-07-14

申请号：AU2003294886

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR WILLIAM ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：AU2003293828A8

公开(公告)日：2004-07-09

申请号：AU2003293828

申请日：2003-12-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：DE10118196A1

公开(公告)日：2002-10-24

申请号：DE10118196

申请日：2001-04-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  GOGL DIETMAR

IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: The method involves subjecting the TMR memory cell (TMR) to a transient reversible magnetic change while reading an information item by applying a current pulse and comparing the resulting changed current signal with the original current signal. The information is stored in the soft magnetic layer of the TMR cell. The pulse is applied to the write line.

公开(公告)号：DE10062570C1

公开(公告)日：2002-06-13

申请号：DE10062570

申请日：2000-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR

IPC: G11C8/12 ,  G11C11/15 ,  G11C11/14

Abstract: The read and write control circuit has selection transistors provided for each bit line (BL) on both sides of each memory cell connected to respective pairs of read/write amplifiers (AMPH,AMPL) at the bit line ends, each having a current source and a current drain. The read/write amplifiers respond to a write signal, to provide a write current in one or other direction for write-in of a logic 0 or 1 for all bit lines selected by a column select signal applied to a column select line (CS), with read out of the logic 0 or 1 by application of a read signal to a selected memory cell. An Independent claim for a magnetoresistive memory is also included.

公开(公告)号：DE10055936A1

公开(公告)日：2002-05-23

申请号：DE10055936

申请日：2000-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  GOGL DIETMAR ,  LAMMERS STEFAN ,  HOENIGSCHMID HEINZ

IPC: H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C11/14 ,  G11C11/15

Abstract: The device has magnetic memory cells at intersections of a cell field with a matrix of row and column lines. In a write operation the magnetic fields generated by write currents in the lines add at an optional intersection to enable demagnetization of the local memory cell. The shape of the lines is optimized so that the magnetic field component in the plane of the cell field decreases rapidly with increasing distance from the intersection.

公开(公告)号：DE10045042C1

公开(公告)日：2002-05-23

申请号：DE10045042

申请日：2000-09-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  FREITAG MARTIN ,  LAMMERS STEFAN ,  BOEHM THOMAS

IPC: G11C11/14 ,  G11C5/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: Single memory cell fields from memory arrays (A) and peripheral circuits (P) assigned to these are interlaced into each other so that utilizing free corner surfaces in a cross-shaped structure produces a high packing density for a module structure. Rows (1-3) in an MRAM module structure are offset to each other so that in row 2, for example, the peripheral circuits bordering on rows 1 and 3 fit in exactly to the corner surfaces of the memory cell fields in rows 1 and 3.

公开(公告)号：DE60304209T2

公开(公告)日：2006-12-14

申请号：DE60304209

申请日：2003-10-28

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  HOENIGSCHMID HEINZ

IPC: G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

公开(公告)号：DE60304209D1

公开(公告)日：2006-05-11

申请号：DE60304209

申请日：2003-10-28

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  HOENIGSCHMID HEINZ

IPC: G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.