公开(公告)号：DE10005618A1

公开(公告)日：2001-08-30

申请号：DE10005618

申请日：2000-02-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAMMERS STEFAN ,  MANYOKI ZOLTAN ,  HOENIGSCHMID HEINZ ,  BOEHM THOMAS

IPC: G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

Abstract: An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

公开(公告)号：DE10121182C1

公开(公告)日：2002-10-17

申请号：DE10121182

申请日：2001-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAMMERS STEFAN ,  GOGL DIETMAR ,  MUELLER GERHARD

IPC: G11C29/00 ,  G11C11/00

Abstract: The memory has a number of planes (1,2,3) having magnetoresistive memory cell fields combined in the form of a cross point array or transistor array, with redundant magnetoresistive memory cell fields (20) provided on the same chip and distributed above the individual planes of the memory matrix, or provided by one of the planes of the memory array, allowing defective memory cells in one plane to be replaced by redundant memory cells of a different plane.

公开(公告)号：DE10102351A1

公开(公告)日：2002-08-08

申请号：DE10102351

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  LAMMERS STEFAN ,  HOENIGSCHMID HEINZ

IPC: G11C8/00 ,  G11C8/08

公开(公告)号：DE10032271C2

公开(公告)日：2002-08-01

申请号：DE10032271

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.

公开(公告)号：DE10010456A1

公开(公告)日：2001-09-20

申请号：DE10010456

申请日：2000-03-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ ,  LAMMERS STEFAN

IPC: G11C11/22 ,  G11C5/14

Abstract: The reference voltage generation device uses reference cells (R1T,R2T ; R1C,R2C) within the ferroelectric memory provided with a logic "0" and a logic "1", at the ends of the word lines (WLT,WLC) along a reference bit line (BLTREF1, BLTREF2 ; BLCREF1,BLCREF2). The ferroelectric memory may be provided via a MOS technology, with a pulsed plate parallel to the bit line for providing a selective-read memory, with a reference or dummy cell at the end of each word line.

公开(公告)号：DE10102351B4

公开(公告)日：2007-08-02

申请号：DE10102351

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANDOLF HELMUT ,  LAMMERS STEFAN ,  HOENIGSCHMID HEINZ

IPC: G11C8/08 ,  G11C8/00

公开(公告)号：DE10011180B4

公开(公告)日：2006-02-23

申请号：DE10011180

申请日：2000-03-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  MANYOKI ZOLTAN ,  LAMMERS STEFAN ,  KANDOLF HELMUT

IPC: G11C29/04 ,  G11C29/00 ,  G11C29/24 ,  G11C29/46

Abstract: A digital circuit configuration includes a memory matrix having M rows and N columns and P

公开(公告)号：DE50104863D1

公开(公告)日：2005-01-27

申请号：DE50104863

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G06F11/20 ,  G11C29/00

Abstract: The invention relates to a configuration for implementing redundancy for a memory chip, in which a fuse bank is connected to a comparator via a redundancy predecoder so that predecoded addresses can be compared with one another in the comparator and undecoded addresses can be stored in the fuse bank. This provides for a low-power and space-saving design.

公开(公告)号：DE10123593C2

公开(公告)日：2003-03-27

申请号：DE10123593

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L27/22 ,  G11C11/14

Abstract: A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed along a first direction and a second direction crossing the former, a multiplicity of electrical lines along the first direction, and a multiplicity of electrical lines along the second direction. The magnetic memory cells in each case are disposed at crossover points of the electrical lines. A first current supply device supplies respectively selected electrical lines along the first direction with current. A second current supply device supplies respectively selected electrical lines along the second direction with current. The second current supply device is configured for setting the direction of the current in accordance with an information item to be written. The first current supply device is suitable for changing over the direction of the current as desired.

公开(公告)号：DE10123593A1

公开(公告)日：2002-11-28

申请号：DE10123593

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L27/22

Abstract: The arrangement has a field of magnetic memory cells along two mutually perpendicular directions, electrical conductors along both directions with memory cells at the intersection points, first and second current supplies for selectively supplying leads in the first and second directions respectively, whereby the second supply device sets the current direction according to information to be written. The first device changes the current direction. The arrangement has a cell field of magnetic memory cells arranged along first and second mutually perpendicular directions, electrical conductors (3a-3d;4a-4d) along both directions with magnetic memory cells (5aa-5dd) at the intersection points of the conductors, first and second current supplies (6,7) for selectively supplying leads in the first and second directions respectively, whereby the second supply device sets the current direction according to information to be written. The first current supply device changes the direction of the current. AN Independent claim is also included for the following: a magnetic memory cell.