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    22.
    发明专利
    未知

    公开(公告)号：DE69822280T2

    公开(公告)日：2005-02-24

    申请号：DE69822280

    申请日：1998-12-18

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

    IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

    Abstract: Disclosed is a semiconductor memory employing a hierarchical bitline architecture which allows for a widened master bitline pitch as well as low bitline capacitance. In an exemplary embodiment, the memory (30) includes a plurality of memory cells (MC) arranged in rows and columns for storing data. Each column has at least one sense amplifier (SAi), at least one pair of master bitlines (MBLi, MBLi) operatively coupled to the sense amplifier, and at least two pairs of local bitlines (LBL1i, LBL1i, LBL2i, LBL2i), coupled to memory cells and selectively coupled to the sense amplifier. At least one of the local bitline pairs is selectively coupled to the sense amplifier via the master bitline pair. Each master bitline pair has a length shorter than a column length, and the master bitlines are arranged in an interleaved configuration. The pitch of at least a portion of at least some of the master bitlines is greater than the local bitline pitch. The master bitlines may be arranged in either folded or open configurations. The master bitline pitch may be about twice the local bitline pitch.

    24.
    发明专利
    未知

    公开(公告)号：DE60006720T2

    公开(公告)日：2004-09-23

    申请号：DE60006720

    申请日：2000-12-04

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： HANSON R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

    IPC: G11C7/10 ,  G11C7/00

    Abstract: A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted. During an input prefetch, an interrupt may occur causing any received portion of the burst or prefetch to be stored in the array without disturbing memory locations corresponding to the balance or remaining bits of the prefetch.

    25.
    发明专利
    未知

    公开(公告)号：DE60010338D1

    公开(公告)日：2004-06-03

    申请号：DE60010338

    申请日：2000-12-05

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： HANSON R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

    IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  H03K17/22 ,  H03K19/0175

    Abstract: A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.

    26.
    发明专利
    未知

    公开(公告)号：DE10244988A1

    公开(公告)日：2003-05-28

    申请号：DE10244988

    申请日：2002-09-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MUELLER GERHARD ,  REITH ARMIN

    IPC: G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  H01L23/522 ,  H01L27/02

    Abstract: A multi-level signal line architecture having signal line pairs employing vertical twists to reduce couplings noise is disclosed. The signal line pairs are provided with open regions to accommodate offsets of twists of adjacent signal line pairs, thus reducing the line pitch of the signal lines. The open region is formed by removing a portion of the signal line in the upper level and locating that portion on another level above the upper level.

    28.
    发明专利
    未知

    公开(公告)号：DE10061580A1

    公开(公告)日：2002-06-27

    申请号：DE10061580

    申请日：2000-12-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MUELLER GERHARD ,  HOENIGSCHMID HEINZ

    IPC: G11C8/02 ,  G11C11/15 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105

    Abstract: The aim of the invention is to guarantee a high degree of flexibility and a compact construction. To this end, the existing plate conduction device (50) of a memory device (1) which functions on the basis of a hysteresis process is configured to detect the state of a memory capacitor (10) and hence, the information that is stored.

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