公开(公告)号：DE59807589D1

公开(公告)日：2003-04-24

申请号：DE59807589

申请日：1998-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRUENING ULRIKE ,  LEHMANN VOLKER ,  STENGL REINHARD ,  WENDT HERMANN ,  REISINGER HANS

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/13

Abstract: An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating structure has a configuration of pores and a defective region. The pores are disposed outside the defective region in a periodic array, and the periodic array is disturbed in the defective region. A surface of the grating structure is provided with a conductive layer at least in the vicinity of the defective region. A method for producing the optical structure is also provided.

公开(公告)号：AT508475T

公开(公告)日：2011-05-15

申请号：AT01927654

申请日：2001-02-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  MEISTER THOMAS ,  STENGL REINHARD

IPC: H01L29/732 ,  H01L21/331

公开(公告)号：SG155055A1

公开(公告)日：2009-09-30

申请号：SG2007029515

申请日：2003-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOECK JOSEF ,  LACHNER RUDOLF ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  SECK MARTIN ,  STENGL REINHARD

IPC: H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/08

Abstract: Method for producing transistor structure The invention relates to a method for fabricating a transistor structure, comprising at least a first and a second bipolar transistor having different collector widths. The invention is distinguished by the fact that all junctions between differently doped regions have a sharp interface. In this case, by way of example, a first collector region 2.1 is suitable for a high- frequency transistor with high limiting frequencies fT and a second collector region 2.2 is suitable for a high-voltage transistor with increased breakdown voltages. Figure 3c

公开(公告)号：DE10250204B8

公开(公告)日：2008-09-11

申请号：DE10250204

申请日：2002-10-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF ,  SECK MARTIN ,  LACHNER RUDOLF

IPC: H01L21/8222 ,  H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

公开(公告)号：DE10250204B4

公开(公告)日：2008-04-30

申请号：DE10250204

申请日：2002-10-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF ,  SECK MARTIN ,  LACHNER RUDOLF

IPC: H01L21/8222 ,  H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

公开(公告)号：DE10316531A1

公开(公告)日：2004-07-08

申请号：DE10316531

申请日：2003-04-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAEFER HERBERT ,  BOECK JOSEF ,  MEISTER THOMAS ,  STENGL REINHARD

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/167 ,  H01L29/732 ,  H01L29/737

Abstract: The device has a collector region (25) of a first conductor type, a sub-collector region (10) of the first type electrically connected to a first side of the collector region, a base region (30) of a second conductor type on the second side of the collector region, an emitter region (50) of the first conductor type above the base region remote from the collector region and a carbon doped semiconducting region on the first side next to the collector region.

公开(公告)号：DE19821901C2

公开(公告)日：2002-05-08

申请号：DE19821901

申请日：1998-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  GRUENING ULRIKE ,  LEHMANN VOLKER ,  WENDT HERMANN ,  WILLER JOSEF ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

IPC: H01L21/8244 ,  H01L27/11 ,  G11C11/412

Abstract: An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

公开(公告)号：DE19958062A1

公开(公告)日：2001-07-05

申请号：DE19958062

申请日：1999-12-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  MEISTER THOMAS F ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN ,  BOECK JOSEF ,  KLEIN WOLFGANG

IPC: H01L21/331 ,  H01L29/732 ,  H01L27/082

Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

公开(公告)号：DE502004011127D1

公开(公告)日：2010-06-17

申请号：DE502004011127

申请日：2004-03-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOECK JOSEF ,  MEISTER THOMAS ,  STENGL REINHARD ,  SCHAEFER HERBERT

IPC: H01L29/737 ,  H01L21/331 ,  H01L29/08 ,  H01L29/167 ,  H01L29/732

公开(公告)号：DE10318422B4

公开(公告)日：2006-08-10

申请号：DE10318422

申请日：2003-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOECK JOSEF ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  STENGL REINHARD

IPC: H01L29/732 ,  H01L21/331 ,  H01L29/08 ,  H01L29/417

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.