21.
    发明专利
    未知

    公开(公告)号:DE50305969D1

    公开(公告)日:2007-01-25

    申请号:DE50305969

    申请日:2003-06-21

    Abstract: A method for fabricating a short channel field-effect transistor is presented. A sublithographic gate sacrificial layer is formed, as are spacers at the side walls of the gate sacrificial layer. The gate sacrificial layer is removed to form a gate recess and a gate dielectric and a control layer are formed in the gate recess. The result is a short channel field-effect transistor with minimal fluctuations in the critical dimensions in a range below 100 nanometers.

    23.
    发明专利
    未知

    公开(公告)号:DE50203707D1

    公开(公告)日:2005-08-25

    申请号:DE50203707

    申请日:2002-12-10

    Abstract: A resistless lithography method for fabricating fine stiuctures is disclosed. IN an embodiment, a semiconductor mask layer (HM) may be formed on a carrier material (TM, HM') and a selective ion implantation (I) being effected in order to dope selected regions ( 1 ) of the semiconductor mask layer (HM). Wet chemical removal of the non doped regions of the semiconductor mask layer (HM) yields a semiconductor mask which can be used for further patterning. A simple and high precision resistless lithography method for structures smaller than 100 nm is obtained in this way.

    25.
    发明专利
    未知

    公开(公告)号:DE10230696A1

    公开(公告)日:2004-01-29

    申请号:DE10230696

    申请日:2002-07-08

    Abstract: A method for fabricating a short channel field-effect transistor is presented. A sublithographic gate sacrificial layer is formed, as are spacers at the side walls of the gate sacrificial layer. The gate sacrificial layer is removed to form a gate recess and a gate dielectric and a control layer are formed in the gate recess. The result is a short channel field-effect transistor with minimal fluctuations in the critical dimensions in a range below 100 nanometers.

    27.
    发明专利
    未知

    公开(公告)号:DE10163346A1

    公开(公告)日:2003-07-10

    申请号:DE10163346

    申请日:2001-12-21

    Abstract: The invention relates to a resistless lithography method for producing fine structures. According to said method, a semiconductor mask layer (HM) is formed on a carrier material (TM, HM'), and a selective ion implantation (I) is carried out in order to dope selected regions (1) of the semiconductor mask layer (HM). A semiconductor mask which can be used for further structuring is obtained by removing the non-doped regions of the semiconductor mask layer (HM) by means of a wet-chemical process. The invention thus provides a simple and highly precise resistless lithography method for producing structures smaller than 100 nm.

    29.
    发明专利
    未知

    公开(公告)号:DE102008054320A1

    公开(公告)日:2009-06-04

    申请号:DE102008054320

    申请日:2008-11-03

    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

    30.
    发明专利
    未知

    公开(公告)号:DE102008046864A1

    公开(公告)日:2009-04-02

    申请号:DE102008046864

    申请日:2008-09-12

    Abstract: The semiconductor structure (130) has a semiconductor chip (200) that is partially embedded within a support. An inductor (520) is electrically coupled to the semiconductor chip and portion of the inductor overlies in a magnetic region (300) which is outside the boundary of the semiconductor chip. An independent claim is included for manufacturing method of semiconductor structure.

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