公开(公告)号：WO2004053995A2

公开(公告)日：2004-06-24

申请号：PCT/DE0303934

申请日：2003-11-27

Applicant: INFINEON TECHNOLOGIES AG ,  BRASE GABRIELA ,  OSTERMAYR MARTIN ,  RUDERER ERWIN

Inventor： BRASE GABRIELA ,  OSTERMAYR MARTIN ,  RUDERER ERWIN

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/417 ,  H01L21/7684 ,  H01L29/0615

Abstract: The invention relates to a solid-state circuit assembly comprising a semiconductor substrate (1), a first doping area, a second doping area (2), a connection doping area (3), an insulating layer (6) and a planarised conductive structure (4, 5). A discharge doping area (7) which is formed in the first and second doping areas (1, 2) makes it possible to reliably remove charge carriers which are produced during planarisation, thereby avoiding a dendrite formation.

Abstract translation: 本发明涉及一种半导体集成电路器件，包括在半导体基板（1），第一掺杂区，第二掺杂区（2），连接掺杂区（3），绝缘层（6）和一对被平坦化导电结构（4，5），其特征在于 通过在第一和第二掺杂区域（1,2）中形成的电荷掺杂区域（7），平坦化期间形成的电荷载流子可以可靠地消散并防止枝晶形成。

公开(公告)号：DE102008054320A1

公开(公告)日：2009-06-04

申请号：DE102008054320

申请日：2008-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  BAUMGARTNER PETER ,  BENETIK THOMAS ,  KALTALIOGLU ERDEM ,  RIESS PHILIPP ,  RUDERER ERWIN ,  TEWS HELMUT ,  GLASOW ALEXANDER VON

IPC: H01L27/08 ,  H01L21/822

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

公开(公告)号：DE10257682A1

公开(公告)日：2004-07-08

申请号：DE10257682

申请日：2002-12-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUDERER ERWIN ,  OSTERMAYR MARTIN ,  BRASE GABRIELA

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/417 ,  H01L23/522 ,  H01L21/28

公开(公告)号：DE10217567A1

公开(公告)日：2003-11-13

申请号：DE10217567

申请日：2002-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENETIK THOMAS ,  RUDERER ERWIN

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/522 ,  H01L27/08 ,  H01L21/768

Abstract: A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).

公开(公告)号：DE102005049793B3

公开(公告)日：2007-07-05

申请号：DE102005049793

申请日：2005-10-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUDERER ERWIN ,  LUTZ WALTHER

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/336

Abstract: A process of manufacturing a semiconductor circuit includes providing a substrate layer, forming a metal layer above the substrate layer, incorporating circuit components in the substrate layer, and electrically connecting the circuit components to the metal layer. The process includes configuring the circuit components to perform an electrical function of the semiconductor circuit. The semiconductor circuit has a specific electrical conductivity between the substrate layer and the metal layer based on the electrical function performed. The process includes increasing the electrical conductivity between the substrate layer and the metal layer compared with the specific electrical conductivity.

公开(公告)号：DE19945939A1

公开(公告)日：2001-04-12

申请号：DE19945939

申请日：1999-09-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AUGUSTIN ANDREAS ,  BARTH HANS-JOACHIM ,  DRAHL CLAUS ,  RUDERER ERWIN ,  PENKA SABINE

IPC: H01L21/02 ,  H01L27/08 ,  H01L21/822 ,  H01L29/92

Abstract: Integrated semiconductor circuit includes a second dielectric layer (D2) which lies in the opening of a first dielectric layer (D1) and is planar to a first conducting layer (M1). Integrated semiconductor circuit has a first conducting layer (M1), a first dielectric layer (D1) and a second conducting layer (M2) arranged on a semiconductor substrate. The first dielectric layer has an opening in the region of a capacitor surface (F). A second dielectric layer (D2) is arranged in the first dielectric layer and is thinner than the first layer. The second dielectric layer in the opening runs along the first conducting layer and planar to it. An Independent claim is also included for a process for the production of the integrated semiconductor circuit comprising: applying a first conducting layer (M1), a first dielectric layer (D1) and a second conducting layer (M2) onto a semiconductor substrate; removing the first dielectric layer in the region of a capacitor surface; and applying a second dielectric layer in the openings formed. The second dielectric layer is applied directly on the first layer in the region of the capacitor surface.

公开(公告)号：DE102008054320B4

公开(公告)日：2015-03-05

申请号：DE102008054320

申请日：2008-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM DR ,  BAUMGARTNER PETER ,  BENETIK THOMAS ,  KALTALIOGLU ERDEM ,  RIESS PHILIPP ,  RUDERER ERWIN ,  TEWS HELMUT ,  GLASOW ALEXANDER VON

IPC: H01L21/822 ,  H01L27/08

Abstract: Verfahren zum Herstellen eines Kondensators (360), wobei das Verfahren folgendes aufweist: Ausbilden einer ersten Platte (310a) und einer zweiten Platte (310b) über einem Werkstück; und Ausbilden eines Kondensatordielektrikums (324a, 324b, 324c) zwischen der ersten Platte (310a) und der zweiten Platte (310b), wobei das Ausbilden der ersten Platte (310a) und der zweiten Platte (310b) jeweils folgendes aufweisen: Bilden mehrerer erster in horizontaler Richtung verlaufender paralleler leitender Elemente (312); Ausbilden mehrerer zweiter in horizontaler Richtung verlaufender paralleler leitender Elemente (314) über den mehreren ersten parallelen leitenden Elementen (312); Koppeln eines ersten Basiselements (316) an ein Ende mindestens einiger der mehreren ersten parallelen leitenden Elemente (312); Koppeln eines zweiten Basiselements (318) an ein Ende von mindestens einigen der mehreren zweiten parallelen leitenden Elemente (314); und Ausbilden mindestens eines verbindenden Elements (320) zwischen den mehreren ersten parallelen leitenden Elementen (312) und den mehreren zweiten parallelen leitenden Elementen (314), wobei das Ausbilden des mindestens einen verbindenden Elements (320) das Ausbilden mindestens eines in horizontaler Richtung länglichen Vias (322) aufweist und wobei das Ausbilden der ersten Platte (310a) und der zweiten Platte (310b) das Verschachteln der mehreren ersten parallelen leitenden Elemente (312) der ersten Platte (310a) mit den mehreren ersten parallelen leitenden Elementen (312) der zweiten Platte (310b) und das Verschachteln der mehreren zweiten parallelen leitenden Elemente (314) der ersten Platte (310a) mit den mehreren zweiten parallelen leitenden Elementen (314) der zweiten Platte (310b) aufweist, wobei die mehreren ersten parallelen leitenden Elemente (312) und die ersten Basiselemente (316) in einem ersten Isoliermaterial (324a) ausgebildet werden, wobei das Ausbilden der verbindenden Elemente (320) und der zweiten parallelen leitenden Elemente (314) das Ausbilden eines zweiten Isoliermaterials (324b, 324c) mit einem unteren Abschnitt und einem oberen Abschnitt über dem ersten Isoliermaterial ...

公开(公告)号：DE50307293D1

公开(公告)日：2007-06-28

申请号：DE50307293

申请日：2003-03-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BENETIK THOMAS ,  RUDERER ERWIN

IPC: H01L23/522 ,  H01L27/04 ,  H01L21/822

Abstract: A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).