公开(公告)号：DE102005001894A1

公开(公告)日：2006-08-03

申请号：DE102005001894

申请日：2005-01-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WALLNER PAUL ,  GREGORIUS PETER ,  SCHLEDZ RALF

IPC: H03M9/00 ,  G11C19/00

Abstract: The synchronous parallel-series converter has first shift register (SRod) which accepts odd-numbered part (D1od(1/8)) of input signal synchronously to rear and front flank of the clock pulse (clkhri) with a first load signal (odloadi) and lets it serially pass as first one-bit signal sequence (D2od(1/2)). A second shift register (SRev) accepts an even-numbered part (D1ev(1/8)) of input signal synchronously to front or rear flank of the clock pulse with a second load signal (evloadi) and lets it serially pass as a second one-bit signal sequence (D2ev(1/2)). A fusion unit (M) accepts the first one-bit signal sequence from first shift register and second one-bit signal sequence from the second shift register. The clock pulse and the first one-bit signal sequence merges synchronously with the rear or front flank of the clock pulse. The second one-bit signal sequence merges synchronously with the front or rear flank of the clock pulse to output signal (D3(1/1)). An independent claim is also included for the use of the synchronous parallel-series converter.

公开(公告)号：DE102005055185A1

公开(公告)日：2006-06-08

申请号：DE102005055185

申请日：2005-11-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  BACHA ABDALLAH ,  SICHERT CHRISTIAN ,  SAVIGNAC DOMINIQUE ,  GREGORIUS PETER ,  WALLNER PAUL

IPC: G11C7/22

Abstract: A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

公开(公告)号：DE10215087B4

公开(公告)日：2004-08-19

申请号：DE10215087

申请日：2002-04-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  PRETE EDOARDO ,  WALLNER PAUL

IPC: H03L7/091 ,  H04L7/00 ,  H04L7/033 ,  H03K5/26

Abstract: A reference signal (6) is scanned within a period of a regulating signal at specific scan time points (S1-S5). By relying on all scan actions (A0-A4) for the reference signal taken within the regulating signal period, output signals (PD0-PD3) are generated so as to assume one of three conditions and are suppressed in the event of a fault. An Independent claim is also included for a device.

公开(公告)号：DE10215087A1

公开(公告)日：2003-10-30

申请号：DE10215087

申请日：2002-04-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  PRETE EDOARDO ,  WALLNER PAUL

IPC: H03L7/091 ,  H04L7/00 ,  H04L7/033 ,  H03K5/26

Abstract: A reference signal (6) is scanned within a period of a regulating signal at specific scan time points (S1-S5). By relying on all scan actions (A0-A4) for the reference signal taken within the regulating signal period, output signals (PD0-PD3) are generated so as to assume one of three conditions and are suppressed in the event of a fault. An Independent claim is also included for a device.

公开(公告)号：DE102014107756A1

公开(公告)日：2014-12-04

申请号：DE102014107756

申请日：2014-06-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： METZNER DIETER ,  RICKES THOMAS ,  WALLNER PAUL ,  WIDERIN PETER

IPC: H04L12/40

Abstract: Es wird eine elektrische Schaltung zum Treiben eines Busses beschrieben, welche wenigstens einen Zweig, der mit wenigstens einer Signalleitung an einem Abschluss des Busses gekoppelt ist, und einen Sendedateneingang umfasst, der ausgelegt ist, Daten zu empfangen, welche die elektrische Schaltung über den Bus treibt. Die elektrische Schaltung umfasst außerdem eine Stromdetektionseinheit, die mit dem wenigstens einen Zweig gekoppelt ist, die dafür ausgelegt ist, einen Strom durch den wenigstens einen Zweig zu detektieren. Die elektrische Schaltung umfasst außerdem eine Überstrombestimmungseinheit, die sowohl mit der Stromdetektionseinheit als auch dem Sendedateneingang gekoppelt ist. Die Überstrombestimmungseinheit ist ausgelegt, einen Überstromzustand des wenigstens einen Zweigs auf der Basis des Stroms an dem wenigstens einen Zweig und der Daten am Sendedateneingang zu bestimmen.

公开(公告)号：DE102006041785B3

公开(公告)日：2008-04-17

申请号：DE102006041785

申请日：2006-09-06

Applicant: QIMONDA AG ,  INFINEON TECHNOLOGIES AG

Inventor： SCHOENAUER TIM ,  WALLNER PAUL ,  DUDHA CHAITANYA

IPC: H03M9/00 ,  G11C7/10 ,  G11C11/4093

公开(公告)号：DE102006019423A1

公开(公告)日：2007-03-15

申请号：DE102006019423

申请日：2006-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WALLNER PAUL ,  SCHLEDZ RALF ,  GREGORIUS PETER ,  RUCKERBAUER HERMANN

IPC: G06F12/00 ,  G11C7/10

Abstract: A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.

公开(公告)号：DE102005007600A1

公开(公告)日：2006-08-24

申请号：DE102005007600

申请日：2005-02-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WALLNER PAUL ,  GREGORIUS PETER

IPC: G11C7/22 ,  G11C11/4076

Abstract: The controller has a cut-off medium (11) that cuts-off an output of clock signals and control signals optionally, when activation/deactivation signal accepts its deactivation condition. A synchronization and actuation medium (12) actuates the output of the clock signals to the point of time synchronous with the next following flank of basic timing signal directly, where activation/deactivation signal accepts its deactivation condition.

公开(公告)号：DE102005042269A1

公开(公告)日：2006-04-13

申请号：DE102005042269

申请日：2005-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  RUCKERBAUER HERMANN ,  SAVIGNAC DOMINIQUE ,  SICHERT CHRISTIAN ,  WALLNER PAUL

IPC: G11C7/22

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.