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公开(公告)号:GB2344694A
公开(公告)日:2000-06-14
申请号:GB9929376
申请日:1999-12-10
Applicant: LUCENT TECHNOLOGIES INC
Inventor: KIZILYALLI ISIK C , MERCHANT SAILESH MANSINH , ROY PRADIP KUMAR , WONG YIU-HUEN
IPC: H01L27/108 , H01L21/02 , H01L21/285 , H01L21/82 , H01L21/8242
Abstract: Tungsten nitride (WN) and/or tungsten silicide nitride (WSiN) diffusion barrier layers are situated between a titanium electrode and a tantalum pentoxide (Ta 2 O 5 ) dielectric layer of a DRAM capacitor. The diffusion barrier layer(s) prevent reaction between the titanium electrode and the tantalum pentoxide during thermal processing of the device structure.
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公开(公告)号:GB2344693A
公开(公告)日:2000-06-14
申请号:GB9929374
申请日:1999-12-10
Applicant: LUCENT TECHNOLOGIES INC
Inventor: KIZILYALLI ISIK C , MERCHANT SAILESH MANSINH , ROY PRADIP KUMAR
IPC: H01L29/78 , C23C14/06 , H01L21/28 , H01L21/283 , H01L21/285 , H01L21/336 , H01L29/49 , H01L29/51
Abstract: A method of manufacturing a silicon gate field effect transistor, characterised by depositing a multilayer gate electrode layer over the dielectric layer, wherein the multilayer gate electrode includes a composite layer comprising tungsten silicide nitride 17 and an electrical conductor 18. The multilayer gate is formed over a tantalum pentoxide dielectric layer 13 which is situated over a silicon substrate 11 in selected device regions. The electrical conductor is preferably made from tungsten silicide however, aluminium and copper may be deposited in addition to or instead of the tungsten silicide. The tungsten silicide nitride/electrical conductor reduces oxygen depletion effects in the tantalum pentoxide. The layers are preferably formed in situ in a PVD apparatus.
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公开(公告)号:GB2351844A
公开(公告)日:2001-01-10
申请号:GB0014433
申请日:2000-06-13
Applicant: LUCENT TECHNOLOGIES INC
Inventor: KIZILYALLI ISIK C , MA YI , MERCHANT SAILESH MANSINH , ROY PRADIP KUMAR
IPC: H01L21/336 , H01L21/02 , H01L21/28 , H01L29/51 , H01L29/94 , H01L21/283
Abstract: An integrated circuit has a dielectric material layer 102, 103 disposed over a substrate 101. The dielectric layer 102, 103 has an equivalent electrical thickness of 2.5 nm or less, relative to silicon dioxide. The dielectric material 102, 103, includes at least one layer other than silicon dioxide. There is an electrode 104 which may consist of W, W x Si y , WSi x N y , TaSi x N y , MoSi x N y , Ma, Ta, or Ti, disposed over the dielectric layer 102, 103. The dielectric layer 102, 103 may comprise an oxide layer 102 grown on the substrate 101 and a high-k dielectric material 103. The high-k dielectric may be Ta 2 O 5 , ZrO 2 , TiO 2 or a pervoskite material, which can be disposed on the grown oxide layer 102. The substrate 101 may be an oxidizable layer, and a stress free oxide layer 105 may be disposed between the oxidizable layer 101 and the grown oxide layer 102. The high-k dielectric layer 103 may be doped with nitrogen. The integrated circuit may be a DRAM, FLASH, or an analog or mixed signal CMOS circuit.
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公开(公告)号:GB2351843A
公开(公告)日:2001-01-10
申请号:GB0013885
申请日:2000-06-07
Applicant: LUCENT TECHNOLOGIES INC
Inventor: KIZILYALLI ISIK C , MASTRAPASQUA MARCO
IPC: H01L29/772 , C23C14/08 , C23C14/58 , H01L21/02 , H01L21/28 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/51 , H01L29/76
Abstract: An electronic device comprises a substrate 301, on to which is deposited a first barrier layer 302, on to which is deposited a second barrier layer303, on to which is deposited a third layer 304. The layers are arranged such that hot carriers are injected across the first barrier layer 302 to the said third layer 304. The electronic device may be a charge injection transistor in which the substrate 301 is silicon and the first barrier layer 302 is SiO 2 and the second barrier layer 303 is a high-k dielectric. The high-k barrier layer may be 3 - 100 nm thick and formed of Ta 2 O 5 , TiO 2 , ZrO 2 and perovskite materials. The SiO 2 layer may be grown on the silicon substrate layer 301 to a thickness of 0.6 - 2 nm in which 0.3 - 0.8 thickness of the said layer may be stress-free. The said third layer 304 may be the collector electrode. Also disclosed is an electronic device comprising a substrate, on to which is disposed a first barrier layer, on to which is disposed a second barrier layer, in which the first barrier layer has a conduction band energy level that is more than 0.5 electron volts greater than that of the second barrier layer. The device is intended to provide a thin first barrier layer which aids the tunnelling of hot carriers and a thick second barrier layer which reduces leakage current. The device may be produced using conventional silicon processing technology.
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25.
公开(公告)号:GB2372150B
公开(公告)日:2003-09-10
申请号:GB0211288
申请日:2000-11-27
Applicant: LUCENT TECHNOLOGIES INC
Inventor: BOULIN DAVID M , FARROW REGINALD C , KIZILYALLI ISIK C , MKRTCHYAN MASIS , LAYADI NACE
IPC: H01J37/304 , H01L23/544
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公开(公告)号:GB2351844B
公开(公告)日:2002-03-20
申请号:GB0014433
申请日:2000-06-13
Applicant: LUCENT TECHNOLOGIES INC
Inventor: KIZILYALLI ISIK C , MA YI , MERCHANT SAILESH MANSINH , ROY PRADIP KUMAR
IPC: H01L21/336 , H01L21/02 , H01L21/28 , H01L29/51 , H01L29/94 , H01L21/283
Abstract: The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.
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27.
公开(公告)号:GB2363903A
公开(公告)日:2002-01-09
申请号:GB0028873
申请日:2000-11-27
Applicant: LUCENT TECHNOLOGIES INC
Inventor: KIZILYALLI ISIK C , SINGH RANBIR , STIRLING LORI
IPC: H01L27/092 , H01L21/28 , H01L21/8238 , H01L27/105 , H01L29/49
Abstract: A method of manufacturing a semiconductor device 100 comprises, forming a first gate electrode 155, a first metal gate electrode material having a work function compatible with a first transistor 115, and forming a second gate electrode 160 of a second metal gate electrode material having a work function compatible with a second transistor 120. The first and second transistors 115, 120 are of opposite types and are formed on a semiconductor substrate. In a semiconductor device 100 the first metal gate electrode material 162b is located over the second metal gate electrode material 162a. The first gate electrode may be formed from a material having a work function of about 4.2 eV and the second gate electrode may be formed from a material having a work fuction of 5.2 eV. The first electrode gate material may be tantalum, tungsten, titanium, or titanium nitride, and the second electrode gate material may be tungsten silicide. The semiconductor device may have at least one n+ doped polysilicon electrode (Figures 7, 8 and 9). There may be a metal etch barrier layer having a high dielectric constant formed from tantalum pentoxide, silicon nitride or aluminium oxide. An integrated circuit includes the semiconductor device and has interconnnects electrically connecting the transistors.
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公开(公告)号:GB2344693B
公开(公告)日:2001-09-12
申请号:GB9929374
申请日:1999-12-10
Applicant: LUCENT TECHNOLOGIES INC
Inventor: KIZILYALLI ISIK C , MERCHANT SAILESH MANSINH , ROY PRADIP KUMAR
IPC: H01L29/78 , C23C14/06 , H01L21/28 , H01L21/283 , H01L21/285 , H01L21/336 , H01L29/49 , H01L29/51
Abstract: The specification describes a process for making gate electrodes for silicon MOS transistor devices having tantalum pentoxide gate dielectrics. The gate electrode includes a layer of tungsten silicide, and, preferably a layer of tungsten suicide nitride. The tungsten silicide nitride/tungsten silicide reduces oxygen depletion effects in the tantalum pentoxide. The layers are preferably formed in situ in a PVD apparatus.
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