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公开(公告)号：BR0211166A
公开(公告)日：2004-09-28
申请号：BR0211166
申请日：2002-07-16
Applicant: QUALCOMM INC
Inventor： CHALLA RAGHU , KASTURI NITIN , SCHLEGEL NIKOLAI
Abstract: The invention is directed toward a digital VGA that is implemented in the logarithmic domain. The digital VGA exploits logarithmic properties to replace a complex multiplier of a conventional digital VGA with a simple and inexpensive adder. Moreover, additional techniques are described to significantly reduce the size of one or more lookup tables (LUTs) implemented within the digital VGA. In this manner, the invention can realize a simple, low cost digital VGA.
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公开(公告)号：HK1053201A1
公开(公告)日：2003-10-10
申请号：HK03105374
申请日：2003-07-25
Applicant: QUALCOMM INC
Inventor： AGRAWAL AVNEESH , SIH GILBERT , ROH MARK , BUTLER BRIAN , CHALLA RAGHU
IPC: H04B1/712 , H04B1/7073 , H04B1/7087 , H04B1/7115 , H04B1/7117 , H04L27/00 , H04B , H04L
Abstract: A method and apparatus for frequency tracking is described. The present invention provides a tracking mechanism for removing the effects of error due to frequency offset as well as compensation for frequency error due to doppler in a plurality of multipath signals. Each finger of a RAKE receiver utilizing the present invention will compute a frequency error for that finger. The weighted average of all of these frequency errors is calculated and filtered to provide a control signal for varying the frequency of IF and RF frequency synthesizers, accounting for the common frequency offset seen at each finger. Additionally, each finger is equipped with a rotator for providing frequency adjustment specific to that finger. The frequency of each finger is adjusted through feedback of the frequency error for that finger.
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公开(公告)号：AU2003208909A1
公开(公告)日：2003-09-02
申请号：AU2003208909
申请日：2003-01-31
Applicant: QUALCOMM INC
Inventor： BLACK PETER J , CHALLA RAGHU
IPC: H04B1/707 , H04L27/00 , H04L27/233 , H04L27/26
Abstract: Techniques for deriving interpolated pilot symbols for a gated pilot in a wireless (e.g., IS-856, cdma2000, or W-CDMA) communication system. In one method, first and second recovered pilot symbols for first and second time instances, respectively, are initially obtained (e.g., derived based on pilot bursts for the gated pilot). A phase change induced in the received signal at a third time instance between the first and second time instances is estimated. First and second phase-rotated symbols are next derived based on the first and second recovered pilot symbols and the estimated induced phase change. Interpolated pilot symbols between the first and third time instances are then derived (e.g., using linear interpolation) based on the first recovered pilot symbol and the first phase-rotated symbol. Similarly, interpolated pilot symbols between the third and second time instances are derived based on the second phase-rotated symbol and the second recovered pilot symbol.
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公开(公告)号：AU2002320604A1
公开(公告)日：2003-03-03
申请号：AU2002320604
申请日：2002-07-16
Applicant: QUALCOMM INC
Inventor： RAGHUPATHY ARUN , CHALLA RAGHU , SINDHUSHAYANA NAGABHUSHANA T
Abstract: In one embodiment, the invention is directed toward techniques for generating results in a logarithmic domain. The techniques may exploit properties of a logarithmic function to reduce the memory requirements needed to implement lookup tables. For example, the techniques may utilize non-uniform sampling over a logarithmic or logarithmic-like function to reduce the number of entries needed for a given lookup table. In particular, the techniques may involve separating a number into an exponent component and a mantissa component. Each of these different components can then be converted from a first domain to a second domain using different lookup tables.
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公开(公告)号：AU2002246929A1
公开(公告)日：2002-08-06
申请号：AU2002246929
申请日：2002-01-04
Applicant: QUALCOMM INC
Inventor： SIH GILBERT C , CHALLA RAGHU
IPC: H04L27/38 , H04B1/16 , H04L27/00 , H04L27/233
Abstract: According to a disclosed embodiment, a receiver comprising a digital rotator in combination with a frequency error discriminator in a digital automatic frequency control loop is used to arrive at accurate digital values used to calibrate a local oscillation frequency. A frequency error in the oscillation frequency of a local frequency generation loop causes a change in the baseband input signal frequency. The change in the baseband input signal frequency related to the frequency error in the local frequency generation loop can be detected as a phase rotation by the frequency error discriminator. By using the digital automatic frequency control loop, the frequency error introduced by the local frequency generation is determined with accuracy. The frequency error and corresponding control bits are entered into a calibration table. The calibration table may be used to adjust the local oscillation frequency for temperature changes, pilot frequency searching, and quick paging.
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Patent Agency Ranking
公开(公告)号：AU1281699A
公开(公告)日：1999-05-24
申请号：AU1281699
申请日：1998-10-26
Applicant: QUALCOMM INC
Inventor： CHALLA RAGHU , AGASHE PARAG A , SOLIMAN SAMIR S
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公开(公告)号：SG11202006793UA
公开(公告)日：2020-08-28
申请号：SG11202006793U
申请日：2019-02-14
Applicant: QUALCOMM INC
Inventor： ZHOU YAN , LUO TAO , GHEORGHIU VALENTIN ALEXANDRU , CHALLA RAGHU , HE RUHUA , LI YONG , VINTOLA TIMO VILLE
Abstract: Certain aspects of the present disclosure relate to methods and apparatus for providing beam switch latency using communications systems operating according to new radio (NR) technologies. For example, the method generally includes determining a latency associated with a beam switch from a source antenna array module to a target antenna array module when the target module is in a low power mode; and signaling a base station to use the determined latency after sending a command for the beam switch.
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公开(公告)号：BRPI0207274B1
公开(公告)日：2016-07-05
申请号：BR0207274
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： RAGHUPATHY ARUN , WALKER BRETT C , HOLENSTEIN CHRISTIAN , SIH GILBERT C , KANG INYUP , SEVERSON MATTHEW L , PETERZELL PAUL E , CHALLA RAGHU , LI TAO
Abstract: "arquitetura de receptor de conversão direta". uma arquitetura de receptor de conversão descendente direta possuindo um loop de dc para remover o offset de dc a partir das componentes de sinal, um amplificador digital de ganho variável (dvga) para prover uma faixa de ganhos, um loop de controle de ganho automático (agc) para prover controle de ganho para o dvga e circuitos de rf/analógico e uma unidade de interface de barramento serial (sbi) para prover controles para os circuitos de rf/analógico através de um barramento serial. o dvga pode ser projetado vantajosamente e localizado como aqui descrito. o modo operacional do loop de vga pode ser selecionado com base no modo operacional do loop de dc, uma vez que estes dois laops interagem um com o outro. a duração de tempo do loop de dc é operada em um modo de aquisição que pode ser selecionado para ser inversamente proporcional à largura de banda do loop de dc no modo de aquisição. os controles para alguns ou todos os circuitos de rf/analógico podem ser providos através do barramento serial.
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公开(公告)号：CA2723058C
公开(公告)日：2012-12-11
申请号：CA2723058
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INYUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
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公开(公告)号：AT403978T
公开(公告)日：2008-08-15
申请号：AT02702159
申请日：2002-02-06
Applicant: QUALCOMM INC
Inventor： GLAZKO SERGUEI , BLACK PETER , CHALLA RAGHU
IPC: H04B1/7073 , H04B7/26
Abstract: Techniques to search for a gated pilot reference in a wireless communication system. In one method, an overall code space in which the pilot may be found is partitioned into a number of groups of code sets, with each code set representative of all possible chip offsets of a specific PN sequence. The groups are ordered based on the likelihood of detecting the pilot in each of the groups. The groups of code sets are then used to search for the pilot, one group at a time, starting with the group most likely to result in successful pilot acquisition and ending with the group least likely to result in successful pilot acquisition. The search is terminated upon successful acquisition. The pilot search may be performed using detect, dwell, and pull-in substages. The detect substage for one group may be performed in parallel with the pull-in substage for another group.
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