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    ROW DECODER FOR FLASH EEPROM STORAGE DEVICE WHICH CAN ERASE SELECTIVELY SUB-GROUP OF ROW OF SOME SECTOR
    21.
    发明专利
    ROW DECODER FOR FLASH EEPROM STORAGE DEVICE WHICH CAN ERASE SELECTIVELY SUB-GROUP OF ROW OF SOME SECTOR 失效

    公开(公告)号：JPH11232883A

    公开(公告)日：1999-08-27

    申请号：JP33595098

    申请日：1998-11-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

    IPC: G11C16/02 ,  G11C16/08

    Abstract: PROBLEM TO BE SOLVED: To provide a row decoder which can erase selectively one or plural rows of some sector of a memory array of a flash memory device. SOLUTION: A row decoder has plural pre-decoding circuits generating pre- decoding signals and plural final decoding circuits driving each row of arrays, and each pre-decoding circuit has a push-pull output and four parallel paths for signal. A first path 50 drives a pull-up transistor when read-out is performed under low voltage, and a second path 52 drives a pull-up transistor when programming and erasing are performed under positive high voltage. A third path drives a pull-down transistor when read-out and programming are performed under low voltage, and a fourth path drives a pull-down transistor when erasing are performed under negative high voltage. There are two selections that one of the first and the second paths 50, 52 and one of the third and the fourth paths are used in accordance with an operation step.

    24.
    发明专利
    未知

    公开(公告)号：DE60230592D1

    公开(公告)日：2009-02-12

    申请号：DE60230592

    申请日：2002-05-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  LOSAVIO ALDO

    IPC: G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44

    Abstract: The memory device (20) has a memory block (1), formed by a plurality of standard sectors (15) and a redundancy portion (2); a control circuit (3), which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit (7) for the data stored in the memory cells. The correctness verifying circuit (7) is enabled by the control circuit (3) and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion (2) and storing redundancy data in a redundancy-memory stage (5b) in the presence of an incorrect datum. Various solutions are presented that implement column, row and sector redundancy, both in case of erasing and programming.

    28.
    发明专利
    未知

    公开(公告)号：DE69935919D1

    公开(公告)日：2007-06-06

    申请号：DE69935919

    申请日：1999-12-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZAMMATTIO MATTEO ,  MOTTA ILARIA ,  MICHELONI RINO ,  GOLLA CARLA

    IPC: G11C16/30 ,  G11C5/14

    Abstract: A voltage boost device includes a first boost stage (4) and a second boost stage (5) connected to an input terminal and to an output terminal (10), the output terminal (10) supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal (SB) having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage (4) is enabled in presence of the second logic level of the operating condition signal (SB), and is disabled in presence of the first logic level of the operating condition signal (SB); the second boost stage (5) is controlled in a first operating condition in presence of the first logic level of the operating condition signal (SB), and is controlled in a second operating condition in presence of the second logic level of the operating condition signal (SB).

    29.
    发明专利
    未知

    公开(公告)号：DE60212332T2

    公开(公告)日：2007-06-06

    申请号：DE60212332

    申请日：2002-04-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  LOSAVIO ALDO

    IPC: G11C29/00

    Abstract: The self-repair method for a nonvolatile memory (1) intervenes at the end of an operation of modification, selected between programming and erasing, in the event of detection of just one non-functioning cell (14a, 14c), and carries out redundancy of the non-functioning cell. To this end, the memory array (15) is divided into a basic portion (20), formed by a plurality of memory cells (14a) storing basic data, and into a on-the-field redundancy portion (21), said on-the-field redundancy portion (21) being designed to store redundancy data including a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a purposely designed redundancy replacement circuit (12) and a purposely designed redundancy data verification circuit (7b).

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