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公开(公告)号：DE69323483D1
公开(公告)日：1999-03-25
申请号：DE69323483
申请日：1993-04-06
Applicant: ST MICROELECTRONICS SRL
Inventor： BETTI GIORGIO , MOLONEY DAVID , PORTALURI SALVATORE
Abstract: A variable gain amplifier is composed of a first voltage-to-current amplifier having a fixed gain; a second voltage-to-current amplifier having a variable gain, functioning in parallel to said first amplifier; a gain control and stabilization variable current generator; a current-to-voltage converter. Current output signals produced by said first and second amplifiers and by said variable current generator are summed and the resulting current signal is converted to a voltage signal by said converter.
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公开(公告)号：DE69128987T2
公开(公告)日：1998-06-18
申请号：DE69128987
申请日：1991-06-17
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , VAI GIANFRANCO , ZUFFADA MAURIZIO , BETTI GIORGIO
IPC: H03K19/0175 , H03K19/094 , H03K19/0948
Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).
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公开(公告)号：IT1246467B
公开(公告)日：1994-11-19
申请号：IT2181690
申请日：1990-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
Abstract: Finite-state machine for reliable computing and adjustment systems, which comprises a combinatorial logic (10) connected to a status memory (11) by means of connections which carry future state signals (12) and of connections which carry current state signals (13). The combinatorial logic (10) comprises input terminals (14) for input signals which are external to the finite-state machine and output terminals (15) for output signals generated by the combinatorial logic (10). The finite-state machine furthermore comprises means for comparing the future state signals (12) to at least one reference level (16); the comparison means set an error signal (18) toward means for resetting the finite-state machine and/or the system which includes it.
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公开(公告)号：DE69330957D1
公开(公告)日：2001-11-22
申请号：DE69330957
申请日：1993-11-10
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , GADDUCCI PAOLO , DEMICHELI MARCO , ALINI ROBERTO
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公开(公告)号：DE69427479D1
公开(公告)日：2001-07-19
申请号：DE69427479
申请日：1994-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： BRIANTI FRANCESCO , PISATI VALERIO , ALINI ROBERTO , MOLONEY DAVID
IPC: G05F3/26
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Patent Agency Ranking
公开(公告)号：DE69320630D1
公开(公告)日：1998-10-01
申请号：DE69320630
申请日：1993-09-14
Applicant: ST MICROELECTRONICS SRL
Inventor： BETTI GIORGIO , GADDUCCI PAOLO , MOLONEY DAVID
IPC: H03F1/30 , H03F3/45 , H03K5/1536 , H03K17/13 , H03K17/60
Abstract: The offset of a zero-crossing detector circuit is virtually eliminated by inverting the inputs of the comparator after a certain delay from a detected zero-crossing while storing the output state assumed pursuant the detection of a zero-crossing for an interval of time longer than said delay but shorter than the minimum interval of time occurring between any two successive zero-crossings of the input signal.
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公开(公告)号：IT1250908B
公开(公告)日：1995-04-21
申请号：IT2072890
申请日：1990-06-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , VAI GIANFRANCO , ZUFFADA MAURIZIO , BETTI GIORGIO
IPC: H03K19/0175 , H03K19/094 , H03K19/0948 , H01L
Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).
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公开(公告)号：DE69421072T2
公开(公告)日：2000-04-20
申请号：DE69421072
申请日：1994-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).
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公开(公告)号：DE69327053T2
公开(公告)日：2000-02-24
申请号：DE69327053
申请日：1993-09-21
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , GADDUCCI PAOLO , BETTI GIORGIO , ALINI ROBERTO
Abstract: In a decoder for decoding a serial data stream, employing an extracted base clock signal, synchronous with an input, coded, serial data stream, a fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary clock signal for synthesizing a pre-decoded value produced by a first combinative logic network within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop, a pipelined operation is implemented by momentarily storing the bits that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock the processing by said first combinative network of the n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the raising front of the outpunt sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating spead may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.
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公开(公告)号：DE69421072D1
公开(公告)日：1999-11-11
申请号：DE69421072
申请日：1994-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).
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