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    Method and device for analog programming of flash EEPROM memory cells with autoverify
    21.
    发明公开
    Method and device for analog programming of flash EEPROM memory cells with autoverify 失效
    的方法及装置具有自检快闪EEPROM的存储单元的模拟编程

    公开(公告)号：EP0905712A1

    公开(公告)日：1999-03-31

    申请号：EP97830477.2

    申请日：1997-09-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Canegallo, Roberto ,  Chioffi, Ernestina ,  Gerna, Danilo ,  Rolandi, Pier Luigi

    IPC: G11C27/00

    CPC classification number: G11C27/005

    Abstract: Device for analog programming comprising a current mirror circuit (19) connected to the drain terminals of a cell to be programmed (2) and of a MOS reference transistor (27); an operational amplifier (31) having inputs connected to the drain terminals (13) of the cell (2) and respectively of the MOS transistor (27) and output connected to the control terminal (30) of the MOS transistor. During programming, the control and drain terminals of the cell (2) are biased at corresponding programming voltages and the output voltage of the operational amplifier (31), which is correlated to the current threshold voltage level of the cell (2), is monitored and the programming is interrupted when this output voltage becomes at least equal to a reference voltage correlated to the threshold value desired for the cell.

    Abstract translation: 要被编程装置模拟编程包括连接到电池的漏极端的电流镜电路（19），（2）和一个MOS晶体管参考（27）的; 运算放大器（31）具有输入端连接到所述单元（2）和分别与MOS晶体管（27）和输出连接至所述MOS晶体管的控制端子（30）的漏极端子（13）。 在编程期间，所述细胞（2）的控制极和漏极端在相应的编程电压和运算放大器（31）的输出电压偏置，所有这一切都被关联到该单元的电流阈值电压电平（2）被监控 和编程中断当该输出电压变成至少等于相关期望该小区的阈值的参考电压。

    Data codification method for the writing of non volatile memory cells
    25.
    发明公开
    Data codification method for the writing of non volatile memory cells 审中-公开
    Datenkodierungsverfahren zur Schreibung einesnichflüchtigenSpeichers

    公开(公告)号：EP1067558A1

    公开(公告)日：2001-01-10

    申请号：EP99830438.0

    申请日：1999-07-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Dozza, Davide ,  Canegallo, Roberto ,  Borgatti, Michele

    IPC: G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/10 ,  G11C16/26

    Abstract: It is described a new method to codify the data for the writing of non volatile memory cells (6) included in a memory array (3). The method provides the following steps succession:

    a) data to be memorized are initially sent to a small memory cell matrix (15) which acts as buffer;
    b) a control logic (9) regulates the data flow between an input/output circuitry (8) of said memory array (3) and such small memory cells matrix buffer (15) and it provides to send the data to be memorised to a coder / decoder block (18);
    c) the codified / decodified information by said coder / decoder block (18) is sent to an elaborator (20) which calculates the distance between two successive data combinations;
    d) said control logic (9) indicates to a writing logic (22) the completion of the codification operation of the data to be stored in the memory array (3);
    e) said writing logic (22) effects the programming of the memory array (3) cells (6) on the basis of the result of the calculus effectuated by said elaborator (20).

    Abstract translation: 描述了一种编码用于写入存储器阵列（3）中的非易失性存储器单元（6）的数据的新方法。 该方法提供以下步骤：a）要存储的数据最初发送到作为缓冲器的小型存储单元矩阵（15）; b）控制逻辑（9）调节所述存储器阵列（3）的输入/输出电路（8）与所述小型存储单元矩阵缓冲器（15）之间的数据流，并且其提供将待存储的数据发送到 编码器/解码器块（18）; c）所述编码器/解码器块（18）的编码/解码信息被发送到计算两个连续数据组合之间的距离的精细器（20）; d）所述控制逻辑（9）向写入逻辑（22）指示要存储在存储器阵列（3）中的数据的编码操作的完成; e）所述写入逻辑（22）基于由所述精细器（20）所执行的微积分的结果来影响存储器阵列（3）单元（6）的编程。

    Communication cell for an integrated circuit, chip comprising the communication cell, electronic system including the chip, and test apparatus
    26.
    发明公开
    Communication cell for an integrated circuit, chip comprising the communication cell, electronic system including the chip, and test apparatus 有权
    用于与通信单元的集成电路芯片通信小区，与所述芯片和测试装置的电子系统

    公开(公告)号：EP2341626A2

    公开(公告)日：2011-07-06

    申请号：EP10197444.2

    申请日：2010-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Canegallo, Roberto ,  Cardu, Roberto ,  Scandiuzzo, Mauro ,  Cani, Salvatore Valerio ,  Perugini, Luca

    IPC: H03K19/0185

    CPC classification number: H03K19/0175 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2924/01021 ,  H01L2924/13091

    Abstract: A communication cell (20, 60) for enabling data communication between an integrated circuit (7) and an electronic unit (5) distinct from the integrated circuit, comprising a contact pad unit (53; 73), configured for capacitively coupling, in a first operating condition of said communication cell, to the electronic unit for receiving an input signal (S IN ) from said electronic unit, and for ohmically coupling, in a second operating condition of said communication cell, to the electronic unit for receiving the input signal; a receiver device (22), including signal-amplifying means (32, 34), connected between said contact pad unit and said integrated circuit, configured for receiving the input signal and generating an intermediate signal (S C ) correlated to the input signal; signal-selection means (24) receiving the intermediate signal (S C ), the input signal (S IN ), and providing an output signal (S IN ; S C ) which is the intermediate signal (S C ) during the first operating condition, and the input signal (S IN ) during the second operating condition; and an input stage (6), connectable between the integrated circuit and the output terminal (24d) of the signal-selection means, configured for receiving the output signal (S IN ; S C ) and providing the output signal to the integrated circuit.

    Abstract translation: ，配置为电容性耦合，在一个;用于在集成电路（7）和电子单元（5）从集成电路不同实现数据通信之间，其包括一接触垫部（73 53）的通信小区（20，60） 用于接收输入信号（S IN）从所述电子单元，以及用于在所述通信单元的第二操作条件欧姆耦合到电子单元，用于接收所述输入信号，所述通信单元，向所述电子单元的第一操作条件 ; 一个接收器装置（22），其包括连接所述接触焊盘单元之间的信号放大装置（32，34）和所述集成电路，被配置用于接收输入信号，并在相关的输入信号的中间信号（S C）产生; 信号选择装置（24）接收所述中间信号（SC），所述输入信号（S IN），并在输出信号提供（S IN; SC）所有这是第一操作状态期间的中间信号（SC），和所述 输入信号（S IN）的第二操作状态期间; 并输入级（6），所述集成电路和所述信号选择装置的输出端子（24D）之间连接，配置成用于接收所述输出信号（S IN S C）和提供输出信号到所述集成电路。

    Communication system between independently clocked devices
    27.
    发明公开
    Communication system between independently clocked devices 有权
    公民社会革命

    公开(公告)号：EP2075708A2

    公开(公告)日：2009-07-01

    申请号：EP08022446.2

    申请日：2008-12-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

    IPC: G06F13/40

    CPC classification number: G06F13/4077 ,  H04L25/0266 ,  H04L25/028

    Abstract: The invention relates to a communication system for the connection between timing non correlated synchronous devices of the type comprising at least one transmitter (30) and one receiver (40) inserted between a first and a second voltage reference (Vcc, GND) and connected to each other by means of a transmitting channel (25) in correspondence with respective transmitting (TX) and receiving (RX) terminals. Advantageously according to the invention, the receiver (40) comprises at least one synchronous input stage (41) suitable for receiving on said receiving terminal (RX) a datum (D) and associated with a synchronous output stage (42) suitable for transmitting said datum (D) in a synchronised way with a clock signal (CP) on a synchronised receiving terminal (RXs).
    The invention also relates to a method for transmitting a datum (D) from a transmitter (30) to a receiver (40) interconnected by means of a capacitive channel (25) in a communication system for the connection between independently clocked devices.

    Abstract translation: 本发明涉及一种用于在包括至少一个发射器（30）和插入在第一和第二电压参考（Vcc，GND）之间的一个接收器（40）的类型的定时非相关同步装置之间的连接的通信系统，并且连接到 彼此通过与相应的发送（TX）和接收（RX）终端相对应的电容或电阻信道（25）来实现。 有利地，根据本发明，接收器（40）包括适于在所述接收终端（RX）上接收数据（D）的至少一个同步输入级（41）并与适于发送所述接收器（40）的同步输出级（42）相关联的至少一个同步输入级 数据（D）以与同步接收终端（RX）上的时钟信号（CP）同步的方式。

    Alignment measurement system to determine alignment between chips
    28.
    发明公开
    Alignment measurement system to determine alignment between chips 有权
    系统zur Messung der Ausrichtung zwischen芯片

    公开(公告)号：EP1763078A1

    公开(公告)日：2007-03-14

    申请号：EP05019639.3

    申请日：2005-09-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Canegallo, Roberto

    IPC: H01L25/065

    CPC classification number: G01R31/2891 ,  G01R31/312 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: The present invention relates to a alignment measurement system (100, 101) for measuring alignment between a plurality of chips of a device under test (21), the chips being assembled in a three-dimensional stacking configuration and equipped with at least an integrated capacitive sensor (1, 10), comprising
    - a multiple capacitors structure (2) integrated in said capacitive sensor (1, 10)
    - at least a sensing circuit (8, 8a) connected to said multiple capacitors structure (2) which issues an output voltage (Vout), proportional to a variation of a capacitive value of the multiple capacitors structure (2) of the integrated capacitive sensor (1, 10) of the device under test (21) and corresponding to a measured misalignment between the chips of the device under test (21).

    Abstract translation: 本发明涉及一种用于测量被测设备（21）的多个芯片之间的对准的对准测量系统（100,101），所述芯片组装成三维堆叠配置并且至少配备有集成电容 传感器（1,10），包括 - 集成在所述电容传感器（1,10）中的多个电容器结构（2） - 至少一个连接到所述多个电容器结构（2）的感测电路（8,8a），其发出输出 电压（Vout）与被测器件（21）的集成电容传感器（1,10）的多个电容器结构（2）的电容值的变化成比例，并且对应于所测量的芯片之间的测量的未对准 被测设备（21）。

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