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    Method for multilevel programming of phase change memory cells using a percolation algorithm
    26.
    发明公开
    Method for multilevel programming of phase change memory cells using a percolation algorithm 有权
    用于编程相变存储器单元与使用Perkolationsalgorithmus多个存储器级方法

    公开(公告)号：EP1729303A1

    公开(公告)日：2006-12-06

    申请号：EP05104877.5

    申请日：2005-06-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Pirovano, Agostino

    IPC: G11C11/56

    CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/79

    Abstract: A method and apparatus for programming a phase change memory cell (2) is disclosed. A phase change memory cell (2) includes a memory element (10) of a phase change material having a first state ("11"), in which the phase change material is crystalline and has a minimum resistance level, a second state ("00") in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states with resistance levels there between. The method includes using programming pulses to program the phase change memory cell (2) in either the set, reset, or one of the intermediate states. To program in the intermediate states, a programming pulse creates a crystalline percolation path having an average diameter (D) through amorphous phase change material and a second programming pulse modifies the diameter (D) of the crystalline percolation path to program the phase change memory cell to the proper current level.

    Vertical MOSFET transistor, in particular operating as a selector in nonvolatile memory devices
    27.
    发明公开
    Vertical MOSFET transistor, in particular operating as a selector in nonvolatile memory devices 有权
    Vertikaler MOSFET晶体管Als Auswahl晶体管fürnichtflüchtigeSpeichereinrichtung betrieben

    公开(公告)号：EP1717861A1

    公开(公告)日：2006-11-02

    申请号：EP05425261.4

    申请日：2005-04-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Pirovano, Agostino

    IPC: H01L27/24 ,  H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/7827 ,  G11C13/0004 ,  H01L27/2454 ,  H01L29/42392 ,  H01L29/665 ,  H01L29/66666 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A vertical MOSFET transistor, formed in a body (13) of semiconductor material having a surface and housing a buried conductive region (19) of a first conductivity type; a channel region (29) of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region (26, 35c) of the first conductivity type, arranged on top of the channel region (29) and the buried conductive region (19); a gate insulation region (22), extending at the sides of and contiguous to the channel region (29); and a gate region (23, 35d) extending at the sides of and contiguous to the gate insulation region (22).

    Abstract translation: 一种垂直MOSFET晶体管，形成在具有表面并且容纳第一导电类型的掩埋导电区域（19）的半导体材料的本体（13）中; 布置在所述掩埋导电区域的顶部上的第二导电类型的沟道区域（29）; 布置在沟道区域（29）和掩埋导电区域（19）的顶部上的第一导电类型的表面导电区域（26,35c）; 栅极绝缘区域（22），其在所述沟道区域（29）的两侧延伸; 以及在栅极绝缘区域（22）的侧面延伸并与栅极绝缘区域（22）相邻的栅极区域（23,35d）。

    Phase-change memory device and manufacturing process thereof
    28.
    发明公开
    Phase-change memory device and manufacturing process thereof 有权
    法新社 - 佛罗伦萨

    公开(公告)号：EP1684352A1

    公开(公告)日：2006-07-26

    申请号：EP05425024.6

    申请日：2005-01-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Zuliani, Paola ,  Pellizzer, Fabio ,  Bez, Roberto

    IPC: H01L27/24 ,  H01L45/00 ,  G11C11/34

    CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: Phase-change memory device, wherein memory cells (2) are arranged in rows (7) and columns (6) and form a memory array. The memory cells (2) are formed by a selection device (4) of an MOS type and by a phase-change region (3) connected to the selection device. The selection device (4) is formed by a first conductive region (32) and a second conductive region (33), which extend in a substrate (31) of semiconductor material and are spaced from one another via a channel region (34), and by an isolated control region (36) connected to a respective row (7) and overlying the channel region (34). The first conductive region (32) is connected to a connection line (42) extending parallel to the rows, the second conductive region (33) is connected to the phase-change region (46), and the phase-change region is connected to a respective column (6). The first connection line (42) is a metal interconnection line and is connected to the first conductive region (32) via a source-contact region (40) made as point contact and distinct from the first connection line (42).

    Abstract translation: 相变存储器件，其中存储器单元（2）以行（7）和列（6）排列并形成存储器阵列。 存储单元（2）由MOS型的选择装置（4）和连接到选择装置的相变区域（3）形成。 选择装置（4）由在半导体材料的衬底（31）中延伸并且经由沟道区（34）彼此间隔开的第一导电区域（32）和第二导电区域（33）形成， 以及连接到相应行（7）并且覆盖通道区域（34）的隔离控制区域（36）。 第一导电区域（32）连接到与行平行延伸的连接线（42），第二导电区域（33）连接到相变区域（46），相变区域连接到 相应的列（6）。 第一连接线（42）是金属互连线，并且经由源点接触区域（40）与第一导电区域（32）连接，源极接触区域（40）形成为与第一连接线（42）不同的点接触。

    A memory device with unipolar and bipolar selectors
    29.
    发明公开
    A memory device with unipolar and bipolar selectors 有权
    Speiherannnung mit unipolaren和bipolaren Auswahlschaltungen

    公开(公告)号：EP1640994A1

    公开(公告)日：2006-03-29

    申请号：EP04104595.6

    申请日：2004-09-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Benvenuti, Augusto ,  Vendrame, Loris ,  Zuliani, Paola

    IPC: G11C16/02 ,  G11C11/34

    CPC classification number: G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/79

    Abstract: A memory device is proposed. The memory device includes a plurality of memory cells (P,S), wherein each memory cell includes a storage element (P) and a selector (S) for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element (M) and a bipolar element (D;B). The memory device further includes control means (110s) for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.

    Abstract translation: 提出了一种存储器件。 存储器件包括多个存储器单元（P，S），其中每个存储器单元包括用于在读取操作或编程操作期间选择相应的存储元件的存储元件（P）和选择器（S）。 选择器包括单极元件（M）和双极元件（D; B）。 存储器件还包括控制装置（110s），用于在编程操作期间在读取操作期间使单极元件能够被普遍使能或双极元件。

    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    30.
    发明公开
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    一种用于制造存储器件的方法，特别是相变存储器，所述方法包括硅化

    公开(公告)号：EP1439579A9

    公开(公告)日：2005-02-09

    申请号：EP03425017.5

    申请日：2003-01-15

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

    IPC: H01L21/8234 ,  H01L21/8239

    CPC classification number: H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

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