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    Process for forming a buried cavity in a semiconductor material wafer
    22.
    发明公开
    Process for forming a buried cavity in a semiconductor material wafer 审中-公开
    Herstellungsverfahren eines vergrabenen Hohlraumes in einer Halbleiterscheibe

    公开(公告)号：EP1130631A1

    公开(公告)日：2001-09-05

    申请号：EP00830148.3

    申请日：2000-02-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Erratico, Pietro ,  Sacchi, Enrico ,  Villa, Flavio ,  Barlocchi, Gabriele ,  Corona, Pietro

    IPC: H01L21/308

    CPC classification number: B81C1/00404

    Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer (10), a holed mask (16) having a lattice structure and comprising a plurality of openings (18) each having a substantially square shape and a side with an inclination of 45° with respect to the flat (110) of the wafer; carrying out an anisotropic etch in TMAH of the wafer (10), using said holed mask (16), thus forming a cavity (20), the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapour deposition (CVD) using TEOS, thus forming a TEOS layer (24) which completely closes the openings of the holed mask (16) and defines a diaphragm (26) overlying the cavity (20) and on which a suspended integrated structure can subsequently be manufactured.

    Abstract translation: 该方法包括以下步骤：在半导体材料晶片（10）的顶部上形成具有格子结构的孔掩模（16），并且包括多个开口（18），每个开口（18）均具有大致正方形的形状， 相对于晶片的平面（110）为45°; 使用所述带孔掩模（16）在晶片（10）的TMAH中进行各向异性蚀刻，从而形成空腔（20），其横截面具有倒立的等腰梯形的形状; 并使用TEOS进行化学气相沉积（CVD），由此形成TEOS层（24），该TEOS层完全封闭了孔罩（16）的开口，并且限定了覆盖空腔（20）的隔膜（26） 随后可以制造悬浮综合结构。

    A method of forming structures with buried oxide regions in a semiconductor substrate
    23.
    发明公开
    A method of forming structures with buried oxide regions in a semiconductor substrate 有权
    一种用于在半导体衬底中产生具有掩埋氧化区的结构的过程

    公开(公告)号：EP1067599A1

    公开(公告)日：2001-01-10

    申请号：EP99830442.2

    申请日：1999-07-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Villa, Flavio ,  Barlocchi Gabriele

    IPC: H01L21/762 ,  H01L21/763 ,  H01L21/20

    CPC classification number: H01L21/76208 ,  H01L21/763

    Abstract: A monocrystalline silicon substrate (2) is subjected to the following operations:

    implantation of doping impurities in a high concentration to form a planar region (42) of a first type (n),
    selective anisotropic etching in order to hollow out trenches to a depth greater than the depth of the planar region (42),
    oxidation of the silicon inside the trenches starting a certain distance from the surface of the substrate, until a silicon dioxide plaque (22) is formed, surmounted by residues of strongly-doped silicon,
    epitaxial growth between and on top of the silicon residues to close the trenches and to bring about a redistribution of the doping impurities into the silicon grown to produce a buried region (42') with low resistivity in an epitaxial layer (23) of high resistivity.

    Abstract translation: 将单晶硅基片（2）进行以下操作：在高浓度掺杂杂质的注入，形成第一类型的（一个或多个），选择性的各向异性蚀刻的平面区域（42），以便挖空沟槽的深度 比平面区域的深度（42）时，开始从所述基片的表面有一定的距离的沟槽内的硅，直到二氧化硅斑块（22）形成，由强掺杂硅的残基超越的氧化， 之间和在硅残基的顶部外延生长以关闭所述沟槽和带来的再分布的掺杂杂质的进入生长以产生具有低电阻率的埋入区（42“）在高电阻率的外延层（23）上的硅 ，

    Process for manufacturing a SOI wafer with buried oxide regions without cusps
    24.
    发明公开
    Process for manufacturing a SOI wafer with buried oxide regions without cusps 审中-公开
    一种制造SOI晶片的方法与隐埋氧化物区域没有峰

    公开(公告)号：EP1049155A1

    公开(公告)日：2000-11-02

    申请号：EP99830256.6

    申请日：1999-04-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Villa, Flavio ,  Barlocchi, Gabriele ,  Corona, Pietro

    IPC: H01L21/762 ,  H01L21/32

    CPC classification number: H01L21/02238 ,  H01L21/02299 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76208 ,  H01L21/76248

    Abstract: The process comprises the steps of forming, in a wafer (1) of monocrystalline semiconductor material, trenches (45) extending between, and delimiting laterally, protruding regions (48); forming masking regions (55, 56), implanted with nitrogen ions, the masking regions surrounding completely the tips of the protruding regions (48); and forming retarding regions (57) on the bottom of the trenches (45), wherein nitrogen is implanted at a lower dose than the masking regions. A thermal oxidation is then carried out and starts at the bottom portion of the protruding regions (48) and then proceeds downwards; thereby, a continuous region (65) of buried oxide is formed and is overlaid by non-oxidized regions (60) corresponding to the tips of the protruding regions and forming nucleus regions for a subsequent epitaxial growth. The masking regions (55, 56) and the retarding regions (57) are formed through two sucdessive implants, including an angle implant, wherein the protruding regions (48) shield the bottom portions of the adjacent protruding regions (48), as well as the bottom of the trenches (45), and a is made perpendicularly to the wafer (1).

    Abstract translation: 该方法包括形成的步骤中，在单晶半导体材料，沟槽（45）之间延伸，并且限定尾盘反弹，突出区域（48）的晶片（1）; 上方形成掩蔽区域（55，56）中，用氮离子注入，完全包围掩模区调用突出区域的尖端（48）; 以及在所述沟槽的底部区域阻滞（57）（45）worin氮在低于掩蔽区域低剂量植入。 然后，热氧化被执行并且在突出区域（48）的底部部分开始，然后前进向下; 由此，掩埋氧化物的连续区域（65）形成，并且是由非氧化区域（60）对应于所述突出区域的尖端和用于随后的外延生长形成核的区域覆盖。 掩蔽区域（55，56）和所述延迟区（57）通过两个sucdessive植入物形成，包括在角植入物，worin突出区域（48）屏蔽所述相邻突出区域的底部部分（48），以及 所述沟槽的底部（45），和一个垂直于由所述晶片（1）。

    Formation of buried cavities in a monocrystalline semiconductor wafer
    25.
    发明公开
    Formation of buried cavities in a monocrystalline semiconductor wafer 有权
    在einer einkristallinen Halbleiterscheibe的Herstellung von vergrabenenHohlräumen

    公开(公告)号：EP1043770A1

    公开(公告)日：2000-10-11

    申请号：EP99830206.1

    申请日：1999-04-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Barlocchi, Gabriele ,  Villa, Flavio

    IPC: H01L21/764

    CPC classification number: H01L21/2007 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/76251 ,  H01L21/76262 ,  H01L21/764

    Abstract: The method allows formation of buried cavities in a wafer (25) of monocrystalline semiconductor material. Initially, at least one cavity (21) is formed in a substrate (10) of monocrystalline semiconductor material, by timed TMAH etching silicon, then the cavity is covered with a material inhibiting epitaxial growth (22); finally, a monocrystalline epitaxial layer (26) is grown above the substrate (10) and the cavities (21). Thereby, the cavity (21) is completely surrounded by monocrystalline material. Starting from this wafer, it is possible to form a thin membrane (52). The original wafer (25) must have a plurality of elongate cavities or channels (21), parallel and adjacent to one another. Trenches (44) are then excavated in the epitaxial layer (26), as far as the channels (21), and the dividers between the channels are removed by timed TMAH etching.

    Abstract translation: 该方法允许在单晶半导体材料的晶片（25）中形成掩埋空腔。 首先，通过定时TMAH蚀刻硅在单晶半导体材料的衬底（10）中形成至少一个空腔（21），然后用抑制外延生长的材料（22）覆盖空腔。 最后，单晶外延层（26）生长在基板（10）和空腔（21）之上。 由此，空腔（21）被单晶材料完全包围。 从该晶片开始，可以形成薄膜（52）。 原始晶片（25）必须具有彼此平行并相邻的多个细长空腔或通道（21）。 然后在外延层（26）中挖掘沟槽（44），只要通道（21），并且通过定时TMAH蚀刻去除通道之间的分隔件。

    Process for manufacturing SOI structures
    30.
    发明公开
    Process for manufacturing SOI structures 审中-公开
    Verfahren zur Herstellung von SOI-Strukturen

    公开(公告)号：EP1326272A1

    公开(公告)日：2003-07-09

    申请号：EP01830822.1

    申请日：2001-12-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Villa, Flavio ,  Barlocchi, Gabriele ,  Corona, Pietro

    IPC: H01L21/762 ,  H01L21/316 ,  H01L21/306

    CPC classification number: H01L21/76262 ,  H01L21/31662 ,  H01L21/76208

    Abstract: For manufacturing an SOI substrate, the following steps are carried out: providing a wafer (1) of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity (9) and laterally delimiting a plurality of pillars of semiconductor material (10); and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate (2); an epitaxial layer (11) is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape; and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings (13a) are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings (13a).

    Abstract translation: 为了制造SOI衬底，进行以下步骤：提供半导体材料的晶片（1）; 在所述晶片内部形成多个通道，所述多个通道形成迷宫腔（9）并横向限定多个半导体材料柱（10）; 并氧化半导体材料的柱以形成掩埋绝缘层。 为了形成迷宫腔，首先在衬底（2）中形成沟槽; 生长外延层（11），其封闭顶部的沟槽; 晶片退火以使柱变形并使其呈现最小能量手柄状形状; 并且去除晶片的周边部分以到达迷宫腔，并且在迷宫腔中形成侧入口（13a）。 通过从侧入口（13a）供给氧化流体来进行氧化。

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