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    METHOD FOR INCREASING ACTIVE INDUCTOR OPERATING RANGE AND PEAKING GAIN
    21.
    发明公开
    METHOD FOR INCREASING ACTIVE INDUCTOR OPERATING RANGE AND PEAKING GAIN 审中-公开

    公开(公告)号：EP3371888A1

    公开(公告)日：2018-09-12

    申请号：EP16778502.1

    申请日：2016-09-09

    Applicant: Xilinx, Inc.

    Inventor： NAMKOONG, Jinyung ,  ZHANG, Wenfeng ,  UPADHYAYA, Parag

    IPC: H03K19/0175

    Abstract: Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.

    INTERDIGITATED CAPACITOR HAVING DIGITS OF VARYING WIDTH
    28.
    发明公开
    INTERDIGITATED CAPACITOR HAVING DIGITS OF VARYING WIDTH 审中-公开
    具有数不同宽度的INTER DIGITAL电容器

    公开(公告)号：EP2754189A1

    公开(公告)日：2014-07-16

    申请号：EP12728142.6

    申请日：2012-05-29

    Applicant: Xilinx, Inc.

    Inventor： WU, Zhaoyin, D. ,  UPADHYAYA, Parag ,  JIANG, Xuewen

    IPC: H01L49/02

    CPC classification number: H01L28/86 ,  Y10T29/43

    Abstract: An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor (100) includes a first plurality of conductive digits (110) and a second plurality of conductive digits (110) positioned in an interlocking manner with the first plurality of conductive digits (110), such that an interdigitated structure is formed. The first plurality of conductive digits (110) and the second plurality of conductive digits (110) collectively form a set of digits, where the width of a first digit in the set of digits (110) is non-uniform with respect to a second digit in the set of digits.

    SYMMETRICAL CENTER TAP INDUCTOR STRUCTURE
    29.
    发明公开
    SYMMETRICAL CENTER TAP INDUCTOR STRUCTURE 有权
    INDUKTORSTRUKTUR MIT EINEM SYMMETRISCHEN ZENTRUM

    公开(公告)号：EP2689456A1

    公开(公告)日：2014-01-29

    申请号：EP12702345.5

    申请日：2012-01-12

    Applicant: Xilinx, Inc.

    Inventor： WU, Zhaoyin, D. ,  JIANG, Xuewen ,  UPADHYAYA, Parag ,  JING, Jing ,  WU, Shuxian

    IPC: H01L23/522

    CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An inductor structure (105, 500, 900) implemented within a semiconductor integrated circuit (IC) can include a coil (205, 505, 905) of conductive material that includes a center terminal (140, 510, 910) located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline (225, 535, 935) bisecting the center terminal. The coil can include a first differential terminal (210, 515, 915) and a second differential terminal (215, 520, 920). The inductor structure can include a return line (155, 560, 960) of conductive material positioned on the center line. The inductor structure can include an isolation ring (220, 525, 945) surrounding the coil. The inductor structure can include a patterned ground shield comprising a plurality of fingers (935, 1035) implemented within an IC process layer located between the coil (905) and a substrate (955) of the IC. The inductor structure can include an isolation wall (1 150) comprising a high conductive material formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger of the patterned ground shield.

    Abstract translation: 在半导体集成电路（IC）内实现的电感器结构（105,500,900）可以包括导电材料的线圈（205,505,905），该线圈包括位于中心端的中心端子（140,510,910） 线圈的长度。 线圈可相对于将中心线平分的中心线（225,535,935）对称。 线圈可以包括第一差分端子（210,515,915）和第二差分端子（215,520,920）。 电感器结构可以包括位于中心线上的导电材料的返回线（155,560,960）。 电感器结构可以包括围绕线圈的隔离环（220,525,945）。 电感器结构可以包括图案化的接地屏蔽，其包括在位于线圈（905）和IC的衬底（955）之间的IC处理层内实现的多个指状物（935,1035）。 电感器结构可以包括隔离壁（115），其包括形成为包围线圈和图案化接地屏蔽的高导电材料。 隔离壁可以连接到图案化接地屏蔽的每个手指的一端。

    A MULTIPLE-LOOP SYMMETRICAL INDUCTOR
    30.
    发明公开
    A MULTIPLE-LOOP SYMMETRICAL INDUCTOR 有权
    具有多磨平衡INDUKTOR

    公开(公告)号：EP2628164A1

    公开(公告)日：2013-08-21

    申请号：EP11760636.8

    申请日：2011-09-12

    Applicant: Xilinx, Inc.

    Inventor： KIREEV, Vassili ,  UPADHYAYA, Parag ,  MARLETT, Mark, J.

    IPC: H01F17/00

    CPC classification number: H01F17/0013 ,  H01F2017/0073 ,  Y10T29/4902

    Abstract: A symmetrical inductor includes pairs of half-loops (e.g., 312, 314, 316, 318), first and second terminal electrodes (e.g., 302, 304), and a center-tap electrode (e.g., 310). The half-loop pairs are in respective conductive layers (e.g., 101, 201 ) of an integrated circuit. Each half-loop pair includes a first (e.g., 312, 316) and second half-loop (e.g., 314, 318) in the respective conductive layer. The first and second terminal electrodes are in a first conductive layer, and the center-tap electrode is in a second conductive layer. The first terminal electrode and the center-tap electrode are coupled through a first series combination that includes the first half-loop of each half-loop pair. The second terminal electrode and the center-tap electrode are coupled through a second series combination that includes the second half-loop of each half-loop pair.

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