公开(公告)号：US06954987B2

公开(公告)日：2005-10-18

申请号：US10849478

申请日：2004-05-19

Applicant: Kenneth Daryl Wong ,  Sean L. Bell

Inventor： Kenneth Daryl Wong ,  Sean L. Bell

IPC: H05K3/00 ,  H05K3/34 ,  H05K3/44 ,  H01K3/10

CPC classification number: H05K3/44 ,  H05K3/0061 ,  H05K3/341 ,  H05K2201/09063 ,  H05K2201/09554 ,  H05K2201/10666 ,  H05K2203/1178 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit board assembly employing a solder vent hole adjacent solder filled interconnect vias connecting to a conductive pallet, is disclosed. The solder vent hole allows gases to escape from an otherwise sealed cavity during solder reflow, relieving positive pressure and thereby allowing solder to flow into it. By providing an escape path for trapped air and gases generated during solder paste reflow, the out-gassing pressure and weight of the molten solder is sufficient to allow the solder paste to flow into the cavity.

Abstract translation: 公开了一种印刷电路板组件，其采用与连接到导电托盘的焊料填充的互连通孔相邻的焊剂通气孔。 焊锡通气孔允许气体在回流焊接过程中从另一个密封的空腔中逸出，减轻正压，从而允许焊料流入其中。 通过为焊膏回流期间产生的被捕获的空气和气体提供逃生路径，熔融焊料的排气压力和重量足以使焊膏流入空腔。

公开(公告)号：US20050224961A1

公开(公告)日：2005-10-13

申请号：US11148890

申请日：2005-06-08

Applicant: Donald Farquhar ,  James Herard ,  Michael Klodowski ,  David Questad ,  Der-jin Woan

Inventor： Donald Farquhar ,  James Herard ,  Michael Klodowski ,  David Questad ,  Der-jin Woan

IPC: H01L21/48 ,  H01L23/34 ,  H01L23/373 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4641 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H05K2203/068 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.

Abstract translation: 电子封装和形成方法。 提供具有第一和第二相对表面的导热层。 第一电介质层在加压下被层压在导热层的第一相对表面上，温度在最低温度T 1 1MIN和最高温度T 1MAX之间。 在层压之后，T 1MAX 3将第一介电层的延展性约束至少为D 1。 T 1MAX取决于D 1和在由第一介电层组成的第一电介质材料上。 在加压下将第二电介质层在导热层的第二相对表面上，在最低温度T 2 M 2 N 2和最大温度T 2 MAX之间的温度下层压。 在层压之后，T 2MAX 2将第二介电层的延展性约束为至少D 2。 T 2MAX取决于D 2和在由第二介电层组成的第二电介质材料上。

公开(公告)号：US06899815B2

公开(公告)日：2005-05-31

申请号：US10109792

申请日：2002-03-29

Applicant: Boyd L. Coomer ,  Michael Walk

Inventor： Boyd L. Coomer ,  Michael Walk

IPC: H01L21/48 ,  H05K3/10 ,  H05K3/38 ,  H05K3/44 ,  H05K3/46 ,  H01B13/00

CPC classification number: H01L21/4857 ,  H05K3/107 ,  H05K3/386 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/09554 ,  H05K2203/0315 ,  H05K2203/1142 ,  Y10T29/49126 ,  Y10T29/49128

Abstract: Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.

公开(公告)号：US20040163248A1

公开(公告)日：2004-08-26

申请号：US10784813

申请日：2004-02-24

Applicant: Unicap Electronics Industrial Corporation

Inventor： Jane Lu ,  Paul Wu ,  Ray Chen ,  Scott Chen ,  Jeff Chang

IPC: H05K001/03 ,  H01K003/10

CPC classification number: H05K3/445 ,  H01L23/3677 ,  H01L2924/0002 ,  H05K3/427 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2203/143 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A thermally enhanced face-up BGA substrate consists of a metal (copper) core, layers, dielectric layers, conductive through-core and build-up vias. It is a new and simple structure with better thermal performance, resulting in lower cost and better reliability. Moreover, high degree of flexibility in choice of material and layer counts as well as layer thickness allows for a wide range of applications in packaging and high density printed circuit board.

Abstract translation: 热增强面朝上的BGA衬底由金属（铜）芯，层，电介质层，导电贯通芯和积聚通孔组成。 它是一种新颖简单的结构，具有更好的热性能，从而降低成本，提高可靠性。 此外，在材料和层数以及层厚度的选择方面的高度灵活性允许在包装和高密度印刷电路板中的广泛应用。

公开(公告)号：US06766576B2

公开(公告)日：2004-07-27

申请号：US10435279

申请日：2003-05-09

Applicant: Takayuki Haze ,  Tsuneo Yabuuchi

Inventor： Takayuki Haze ,  Tsuneo Yabuuchi

IPC: H01K310

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/385 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/086 ,  H05K2203/087 ,  H05K2203/1157 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49165

Abstract: The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.

公开(公告)号：US20040134685A1

公开(公告)日：2004-07-15

申请号：US10744142

申请日：2003-12-22

Applicant: International Business Machines Corporation

Inventor： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC: G03G009/00 ,  H05K001/11 ,  H01R012/04

CPC classification number: H05K3/445 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/108 ,  H05K3/426 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0323 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a printed circuit board with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the board including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

Abstract translation: 提供了一种在两个可光成像的电介质层之间形成具有金属功率平面层的印刷电路板的方法。 光刻图形的金属填充通孔和电镀通孔位于光图案化材料中，信号电路位于连接到通孔和电镀通孔的每个介电材料的表面上。 边界可以在板的周围，包括从一个电介质层的边缘终止的金属层。 提供带有间隙孔的铜箔。 第一层和第二层可光成像的可固化电介质材料位于铜的相对两侧。 在可光成像材料的第一层和第二层上形成图案以通过通孔显露金属层。 开发了通孔，在两个电介质层中对其进行图案化。 可光成像材料，通孔和通孔的表面通过镀铜进行金属化，优选使用光致抗蚀剂。

公开(公告)号：US20040132279A1

公开(公告)日：2004-07-08

申请号：US10729174

申请日：2003-12-05

Applicant: International Business Machines Corporation

Inventor： Frank D. Egitto ,  Elizabeth Foster ,  Raymond T. Galasco ,  Voya R. Markovich ,  Manh-Quan Tam Nguyen

IPC: H01L021/4763 ,  H01L021/44

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2203/0733 ,  H01L2924/00

Abstract: The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.

Abstract translation: 通过在层叠到用作接地平面或电源平面的导电金属芯的第一电介质层中提供盲目的无地通孔来改善电子封装的密度和利用堆叠盲孔的子组件的电可靠性。 通过延伸到芯的电介质层提供孔。 使用金属芯作为阴极电解沉积诸如铜的金属，或者无电渗入孔中。 金属沉积在芯上并逐渐建立在孔中以达到通孔所需的深度。 第二电介质层被层压到第一电介质层，并且具有与第一通孔对准的第二层盲孔。 该第二通孔可以由常规电镀技术形成。 可以以这种方式组装具有堆叠的盲孔的多个电介质层。

公开(公告)号：US06744135B2

公开(公告)日：2004-06-01

申请号：US10147073

申请日：2002-05-17

Applicant: Takehiko Hasebe ,  Takehide Yokozuka ,  Nobuyuki Ushifusa ,  Masahide Harada ,  Eiji Matsuzaki ,  Hiroshi Hozoji

Inventor： Takehiko Hasebe ,  Takehide Yokozuka ,  Nobuyuki Ushifusa ,  Masahide Harada ,  Eiji Matsuzaki ,  Hiroshi Hozoji

IPC: H01L2334

CPC classification number: H01L24/16 ,  H01L23/142 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/32057 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/83851 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01054 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/021 ,  H05K1/056 ,  H05K1/144 ,  H05K3/384 ,  H05K3/4608 ,  H05K3/4641 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10734 ,  H01L2924/05432 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides an electronic apparatus having a metal core substrate including a metal plate, an insulating layer formed on the metal plate and a conductive layer formed on the insulating layer, and an electronic part, and to which the conductive layer and a terminal of the electronic part are connected. In the electronic apparatus, a member having a high thermal conductivity is arranged so as to be in contact with both of the metal plate and the electronic part. Accordingly, a heat radiating property of the electronic apparatus is increased.

Abstract translation: 本发明提供一种电子设备，其具有包括金属板的金属芯基板，形成在金属板上的绝缘层和形成在绝缘层上的导电层，以及电子部件，并且导电层和导体层的端子 电子部件连接。 在电子设备中，具有高导热性的部件被布置成与金属板和电子部件两者接触。 因此，电子设备的散热性提高。

公开(公告)号：US20040045159A1

公开(公告)日：2004-03-11

申请号：US10658941

申请日：2003-09-10

Applicant: Tessera, Inc.

Inventor： Thomas H. DiStefano ,  Joseph Fjelstad

IPC: C09J001/00

CPC classification number: H05K3/462 ,  H01L23/49827 ,  H01L23/5385 ,  H01L2924/0002 ,  H01R12/523 ,  H01R12/714 ,  H01R13/2414 ,  H01R43/0256 ,  H05K1/0272 ,  H05K1/036 ,  H05K1/056 ,  H05K1/116 ,  H05K3/0032 ,  H05K3/326 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0554 ,  H05K2203/0582 ,  H05K2203/135 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1744 ,  H01L2924/00

Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact extends from a central conductor, and has a peripheral portion adapted to contract radially inwardly toward the central conductor response to a force applied by a contact pad defining a central hole on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts contract radially inwardly and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by friction welding, or by a conductive bonding material carried on the contacts themselves.

公开(公告)号：US06671950B2

公开(公告)日：2004-01-06

申请号：US09901373

申请日：2001-07-09

Applicant: Lance C. Sturni ,  Kevin C. Olson

Inventor： Lance C. Sturni ,  Kevin C. Olson

IPC: H01K310

CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A process for fabricating a multi-layer circuit assembly is provided comprising the following steps: (a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core; (c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core; (d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core; and (e) applying a resinous photosensitive layer to the metal layer. Additional processing steps such as circuitization may be included. Also provided are multi-layer circuit assemblies produced by the process of the present invention, comprising component layers having high via density and thermal coefficients of expansion that are compatible with those of semiconductor chips and rigid wiring boards which may be attached as components of the circuit assembly.

Abstract translation: 提供一种制造多层电路组件的方法，包括以下步骤：（a）提供具有500至10,000个孔/平方英寸（75至1550个孔/平方厘米）的通孔密度的穿孔导电芯;（b ）在所述导电芯的所有暴露表面上施加电介质涂层以在所述导电芯的所有暴露表面上形成共形涂层;（c）以预定图案烧蚀所述电介质涂层的表面以暴露所述导电芯部分 芯;（d）将金属层施加到所有表面以通过导电芯形成金属化通孔; 另外还可以包括诸如电路化的其它处理步骤。还提供了通过本发明的方法生产的多层电路组件，其包括具有高通孔密度和热量的组分层 与可以作为电路组件的组件附接的半导体芯片和刚性线路板的扩展系数相容。