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    312.
    发明专利
    未知

    公开(公告)号：AT449374T

    公开(公告)日：2009-12-15

    申请号：AT08150756

    申请日：2004-05-06

    Applicant: IBM

    Inventor： HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH ,  SLEGEL TIMOTHY

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10

    Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

    INVALIDACION DE ALMACENAMIENTO, BORRADO DE ELEMENTOS DE LA MEMORIA INTERMEDIA.
    313.
    发明专利
    INVALIDACION DE ALMACENAMIENTO, BORRADO DE ELEMENTOS DE LA MEMORIA INTERMEDIA. 未知

    公开(公告)号：ES2327058T3

    公开(公告)日：2009-10-23

    申请号：ES06116358

    申请日：2004-05-06

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

    IPC: G06F12/10 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08

    Abstract: Un método para invalidar una gama de dos o más elementos de una tabla de traducción de direcciones en un sistema informático que tiene tablas de traducción de direcciones, dispuestas en tablas de segmentos y tablas de regiones, donde un elemento en una tabla de regiones corresponde a una tabla de segmentos, para traducir dinámicamente direcciones virtuales a direcciones de almacenamiento principal, el método comprende los pasos de: determinar la instrucción ejecutable desde un código de operación de una máquina para ser ejecutada, que la instrucción esté configurada para iniciar la ejecución de una operación de invalidación y borrado; y ejecutar la instrucción, comprendiendo el paso de ejecución las etapas de: interpretar la instrucción para identificar una rutina de software determinada para emular la operación de la instrucción en una unidad central de procesamiento subyacente que tiene una arquitectura de conjuntos de instrucciones diferente, la rutina de software predeterminada comprende una pluralidad de instrucciones; ejecutar la rutina de software predeterminada; invalidar (402, 404, 406) la gama de dos o más elementos de una tabla de traducción de direcciones; en la que la gama es especificada como una gama específica de elementos de una tabla de traducción de direcciones.

    314.
    发明专利
    未知

    公开(公告)号：AT382896T

    公开(公告)日：2008-01-15

    申请号：AT04731399

    申请日：2004-05-06

    Applicant: IBM

    Inventor： SLEGEL TIMOTHY ,  HELLER LISA ,  PFEFFER ERWIN ,  PLAMBECK KENNETH

    IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

    Abstract: A method for invalidating translation table entries and clearing corresponding dynamic address translation (DAT) table entries of a translation lookaside buffer (TLB) associated with a processing unit in a computer system, the computer system comprising one or more address translation tables providing translation information to translate virtual addresses to real addresses, wherein address translation table entry information is maintained in the TLB, the method comprising: a) fetching for execution a multifunction Invalidate DAT Table Entry (IDTE) machine instruction, the IDTE instruction comprising an opcode field identifying said instruction and an information field comprising: 1) a first register field for identifying a first register for indicating an origin and type of an address translation table containing a range of one or more entries to be invalidated, 2) a second register field for identifying a second register for including indices used to select a translation table entry in a type of address translation table indicated by the first register, and an option bit for indicating whether a clear by address space control element (ASCE) operation or an invalidating-and-clearing operation is to be performed, and a range field for identifying a number of additional translation table entries, in the address translation table indicated by the first register, to be invalidated, and 3) a third register field for identifying a third register for indicating an origin and type of address translation table to be used when the clear by address space control element operation is to be performed for only selectively clearing TLB entries; and b) executing the fetched IDTE machine instruction, the executing step comprising: i. determining, from the option bit in the second register, whether a clear by address space control element operation is to be performed; ii. responsive to the option bit indicating that the clear by address space control element operation is to be performed, clearing the TLB, independent of the content of the first register, of those entries in which the address translation table origin of a translation table was used to create the entries in the TLB corresponds to the address translation table origin in the third register; iii. responsive to the option bit indicating that the clear by address space control element operation is not to be performed, invalidating the range of address translation table entries of a translation table identified by the range field, and clearing the TLB entries corresponding to the invalidated entries.

    VECTOR PACK AND UNPACK INSTRUCTIONS
    316.
    发明专利
    VECTOR PACK AND UNPACK INSTRUCTIONS 未知

    公开(公告)号：AU2022227809A9

    公开(公告)日：2025-03-06

    申请号：AU2022227809

    申请日：2022-02-18

    Applicant: IBM

    Inventor： SCHWARZ ERIC ,  SLEGEL TIMOTHY ,  BRADBURY JONATHAN ,  KLEIN MICHAEL ,  COPELAND REID ,  GUO XIN

    IPC: G06F9/30

    Abstract: Vector pack and unpack instructions are described. An instruction to perform a conversion between one decimal format and another decimal format is executed, in which the one decimal format or the other decimal format is a zoned decimal format. The executing includes obtaining a value from at least one register specified using the instruction. At least a portion of the value is converted from the one decimal format to the other decimal format different from the one decimal format to provide a converted result. A result obtained from the converted result is written into a single register specified using the instruction.

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